參數(shù)資料
型號(hào): PCD5003AH
廠商: NXP SEMICONDUCTORS
元件分類: 尋呼電路
英文描述: Enhanced Pager Decoder for POCSAG
中文描述: TELECOM, PAGING DECODER, PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁(yè)數(shù): 37/44頁(yè)
文件大?。?/td> 233K
代理商: PCD5003AH
1999 Jan 08
37
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Notes
1.
32768 Hz reference signal: 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods
(pulse duration: t
RFP
). The timing is shown in Fig.15.
50 Hz reference signal: square-wave.
The fall time may be faster than prescribed in the I
2
C-bus specification for very low load capacitance values.
To increase the fall time external capacitance is required.
Duration depends on programmed bit rate; after reset t
ZSU
= 1.5 bits.
Nominal values; pause in 12th data bit (see Table 12).
2.
3.
4.
5.
POCSAG data timing (1200 bits/s)
f
DI
data input rate
SPF byte 01H;
bits D5, D4 = 1 0
1200
bits/s
t
BIT
t
CW
t
PA
t
BAT
bit duration
code-word duration
preamble duration
batch duration
480
833.3
26.7
453.3
μ
s
ms
ms
ms
POCSAG data timing (2400 bits/s)
f
DI
data input rate
SPF byte 01H;
bits D5, D4 = 1 1
2400
bits/s
t
BIT
t
CW
t
PA
t
BAT
bit duration
code-word duration
preamble duration
batch duration
240
416.6
13.3
226.6
μ
s
ms
ms
ms
Synthesizer control
t
ZSU
f
ZSC
t
ZCL
t
ZSD
t
ZDS
t
ZDL1
t
ZLE
t
ZDL2
synthesizer set-up duration
output clock frequency
clock pulse duration
data bit duration
data bit set-up time
data load enable delay
load enable pulse duration
inter block delay
oscillator running; note 4
note 5
1
38400
13.02
26.04
13.02
91.15
13.02
117.19
2
bits
Hz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
note 5
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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