參數(shù)資料
型號: PCD5003AH
廠商: NXP SEMICONDUCTORS
元件分類: 尋呼電路
英文描述: Enhanced Pager Decoder for POCSAG
中文描述: TELECOM, PAGING DECODER, PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁數(shù): 36/44頁
文件大?。?/td> 233K
代理商: PCD5003AH
1999 Jan 08
36
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Receiver control
t
RXT
t
RXON
RXE, ROE transition time
RXE establishment time
(nominal values: actual
duration is bit rate dependent,
see Table 22)
C
L
= 5 pF
SPF byte 01H; bits
D1, D0 = 0 0
D1, D0 = 0 1
D1, D0 = 1 0
D1, D0 = 1 1
SPF byte 01H; bits
D3, D2 = 0 0
D3, D2 = 0 1
D3, D2 = 1 0
D3, D2 = 1 1
100
ns
5
10
15
30
ms
ms
ms
ms
t
ROON
ROE establishment time
(nominal values: actual
duration is bit rate dependent,
see Table 22)
20
30
40
50
ms
ms
ms
ms
I
2
C-bus interface
f
SCL
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
r
t
f
C
B
t
SU;STA
t
HD;STA
t
SU;STO
SCL clock frequency
SCL clock low period
SCL clock HIGH period
data set-up time
data hold time
SDA, SCL rise time
SDA, SCL fall time
capacitive bus line load
START condition set-up time
START condition hold time
STOP condition set-up time
0
1.3
0.6
100
0
note 3
0.6
0.6
0.6
400
300
300
400
kHz
μ
s
μ
s
ns
ns
ns
ns
pF
μ
s
μ
s
μ
s
Reset
t
RST
t
RSU
t
OSU
external reset duration
set-up time after reset
set-up time after switch-on
50
105
4
μ
s
μ
s
ms
oscillator running
oscillator running
Data input
t
TDI
t
DI1
t
DI0
data input transition time
data input logic 1 duration
data input logic 0 duration
see Fig.14
see Fig.14
see Fig.14
t
BIT
t
BIT
100
μ
s
POCSAG data timing (512 bits/s)
f
DI
data input rate
SPF byte 01H;
bits D5, D4 = 0 0
512
bits/s
t
BIT
t
CW
t
PA
t
BAT
bit duration
code-word duration
preamble duration
batch duration
1125
1.9531
62.5
1062.5
ms
ms
ms
ms
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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