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參數(shù)資料
| 型號： | PCA9501 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins |
| 中文描述： | 8位I2C和SMBus I / O口的中斷，2千比特的EEPROM和6個地址引腳 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大小： | 146K |
| 代理商： | PCA9501 |
Philips Semiconductors
8-bit I
2
C and SMBus I/O port with interrupt,
2-kbit EEPROM and 6 address pins
Product data
PCA9501
2003 Sep 12
16
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER
SPECIFICATION
Memory cell data retention
10 years minimum
Number of memory cell write cycles
100,000 cycles minimum
I
2
C-BUS TIMING CHARACTERISTICS
SYMBOL
I
2
C-bus timing
(see Figure 22; Note 1)
PARAMETER
MIN.
TYP.
MAX.
UNIT
f
SCL
t
SW
t
BUF
t
SU;STA
t
HD;STA
t
r
t
f
t
SU;DAT
t
HD;DAT
t
VD;DAT
t
SU;STO
NOTE:
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input
voltage swing of V
SS
to V
DD
.
SCL clock frequency
—
—
400
kHz
tolerable spike width on bus
—
—
50
ns
μ
s
μ
s
μ
s
μ
s
μ
s
ns
bus free time
1.3
—
—
START condition set-up time
0.6
—
—
START condition hold time
0.6
—
—
SCL and SDA rise time
—
—
0.3
SCL and SDA fall time
—
—
0.3
data set-up time
250
—
—
data hold time
0
—
—
ns
μ
s
μ
s
SCL LOW to data out valid
—
—
1.0
STOP condition set-up time
0.6
—
—
PORT TIMING CHARACTERISTICS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
t
pv
t
ps
t
ph
t
iv
t
ir
Output data valid; C
L
≤
100 pF
Input data setup time; C
L
≤
100 pF
Input data hold time; C
L
≤
100 pF
Interrupt input data valid time; C
L
≤
100 pF
Interrupt reset time; C
L
≤
100 pF
—
—
4
μ
s
0
—
—
μ
s
4
—
—
μ
s
—
—
4
μ
s
—
—
4
μ
s
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