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參數資料
| 型號： | PCA9501 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins |
| 中文描述： | 8位I2C和SMBus I / O口的中斷，2千比特的EEPROM和6個地址引腳 |
| 文件頁數： | 10/22頁 |
| 文件大小： | 146K |
| 代理商： | PCA9501 |
Philips Semiconductors
8-bit I
2
C and SMBus I/O port with interrupt,
2-kbit EEPROM and 6 address pins
Product data
PCA9501
2003 Sep 12
10
Read operations
PCA9501 read operations are initiated in an identical manner to
write operations with the exception that the memory slave address
’
R/W bit is set to a one. There are three types of read operations;
current address, random and sequential.
Current Address Read (see Figure 13)
The PCA9501 contains an internal address counter that increments
after each read or write access, as a result if the last word accessed
was at address n then the address counter contains the address
n+1.
When the PCA9501 receives its memory slave address with the
R/W bit set to one it issues an acknowledge and uses the next eight
clocks to transmit the data contained at the address stored in the
address counter. The master ceases the transmission by issuing the
stop condition after the eighth bit. There is no ninth clock cycle for
the acknowledge.
Random Read (see Figure 14)
The PCA9501
’
s random read mode allows the address to be read
from to be specified by the master. This is done by performing a
dummy write to set the address counter to the location to be read.
The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the
acknowledge from the PCA9501 the master reissues the start
condition and memory slave address with the R/W bit set to one.
The PCA9501 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed
location. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
Sequential Read (see Figure 15)
The PCA9501 sequential read is an extension of either the current
address read or random read. If the master doesn
’
t issue a stop
condition after it has received the eighth data bit, but instead issues
an acknowledge, the PCA9501 will increment the address counter
and use the next eight cycles to transmit the data from that location.
The master can continue this process to read the contents of the
entire memory. Upon reaching address 255 the counter will return to
address 0 and continue transmitting data until a stop condition is
received. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
SW00653
S
1
A5
A4
A3
A2
A1
A0
1
A
SDA
ACKNOWLEDGE
FROM SLAVE
R/W
START CONDITION
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
P
STOP
CONDITION
Figure 13. Current Address Read
SW00654
S
P
SDA
1
A5 A4 A3 A2 A1 A0
A
A
0
START
CONDITION
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
A
ACKNOWLEDGE
FROM SLAVE
DATA FROM MEMORY
STOP
CONDITION
S
START
CONDITION
1 A5 A4 A3 A2 A1 A0
1
R/W
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
SLAVE ADDRESS (MEMORY)
Figure 14. Random Read
SW00655
S
P
SDA
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
DATA FROM MEMORY
1
A5 A4 A3 A2 A1 A0
A
A
1
START CONDITION
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
DATA n
A
ACKNOWLEDGE
FROM MASTER
DATA n+X
STOP
CONDITION
DATA n+1
DATA FROM MEMORY
Figure 15. Sequential Read
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| PCA9501A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Smart, simple solutions for the 12 most common design concerns |
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