參數(shù)資料
型號(hào)： PCA8565
廠商： NXP Semiconductors N.V.
英文描述： Real time clock/calender
中文描述： 實(shí)時(shí)時(shí)鐘/ calender
文件頁(yè)數(shù)： 17/26頁(yè)
文件大?。?/td> 581K
代理商： PCA8565
Philips Semiconductors
PCA8565
Real time clock/calender
Product data
Rev. 01 — 31 March 2003
17 of 26
9397 750 10695
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
12. Dynamic characteristics
[1]
[2]
Unspecified for f
CLKOUT
= 32.768 kHz.
All timing values are valid within the operating supply voltage at ambient temperature and referenced to V
IL
and V
IH
with an input voltage
swing of V
SS
to V
DD
.
A detailed description of the I
2
C-bus specification, with applications, is given in brochure The I
2
C-bus and how to use it This brochure
may be ordered using the code 9398 393 40011.
I
2
C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
[3]
[4]
Table 29:
V
DD
= 1.8 to 5.5 V; V
SS
= 0 V; T
amb
=
40 to + 125
°
C; f
osc
= 32.768 kHz; quartz R
s
= 40 k
; C
L
= 8 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Oscillator
C
INT
integrated load
capacitance
f
osc
/f
osc
oscillator stability
V
DD
= 200 mV; T
amb
= 25
°
C
Quartz crystal parameters (f = 32.768 kHz)
R
s
series resistance
C
L
parallel load capacitance
C
T
trimmer capacitance
CLKOUT output
δ
CLKOUT
CLKOUT duty cycle
Timing characteristics: I
2
C-bus
[2][3]
f
SCL
SCL clock frequency
t
HD;STA
START condition hold time
t
SU;STA
set-up time for a repeated
START condition
t
LOW
SCL LOW time
t
HIGH
SCL HIGH time
t
r
SCL and SDA rise time
t
f
SCL and SDA fall time
C
b
capacitive bus line load
t
SU;DAT
data set-up time
t
HD;DAT
data hold time
t
SU;STO
set-up time for STOP
condition
t
SW
tolerable spike width on
bus
Dynamic characteristics
Min
Typ
Max
Unit
15
25
35
pF
-
2
×
10
-7
-
-
-
-
5
-
10
-
40
-
25
k
pF
pF
[1]
-
50
-
%
[4]
-
-
-
-
400
-
-
kHz
μ
s
μ
s
0.6
0.6
1.3
0.6
-
-
-
100
0
0.6
-
-
-
-
-
-
-
-
-
-
0.3
0.3
400
-
-
-
μ
s
μ
s
μ
s
μ
s
pF
ns
ns
μ
s
-
-
50
ns
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PCA8565TS 制造商:PHIL 功能描述:
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