參數(shù)資料
型號(hào): PCA8565
廠商: NXP Semiconductors N.V.
英文描述: Real time clock/calender
中文描述: 實(shí)時(shí)時(shí)鐘/ calender
文件頁數(shù): 11/26頁
文件大?。?/td> 581K
代理商: PCA8565
Philips Semiconductors
PCA8565
Real time clock/calender
Product data
Rev. 01 — 31 March 2003
11 of 26
9397 750 10695
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
3. Clear STOP (control/status 1, bit STOP = 0)
4. Set time registers to desired value
5. Apply 32 clock pulses to CLKOUT
6. Read time registers to see the first change
7. Apply 64 clock pulses to CLKOUT
8. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
8.8 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the
long start-up times experienced by these types of circuits, a mechanism has been
built in to disable the POR and hence speed up on-board test of the device. The
setting of this mode requires that the I
2
C-bus pins, SDA and SCL, be toggled in a
specific order as shown in
Figure 5
. All timings are required minimums.
Once the override mode has been entered, the device immediately stops being reset
and normal operation may commence i.e. entry into the EXT_CLK test mode via
I
2
C-bus access. The override mode may be cleared by writing a logic 0 to TESTC.
TESTC must be set to logic 1 before re-entry into the override mode is possible.
Setting TESTC to logic 0 during normal operation has no effect except to prevent
entry into the POR override mode.
9.
Characteristics of the I
2
C-bus
The I
2
C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor. Data transfer may
be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal (see
Figure 6
).
Fig 5.
POR override sequence.
handbook, full pagewidth
MGM664
SCL
500 ns
2000 ns
SDA
8 ms
override active
power up
相關(guān)PDF資料
PDF描述
PCA8581C 128 x 8-bit EEPROM with I2C-bus interface
PCA8581CP 128 x 8-bit EEPROM with I2C-bus interface
PCA8581CT 128 x 8-bit EEPROM with I2C-bus interface
PCA8581P 128 x 8-bit EEPROM with I2C-bus interface
PCA8581T 128 x 8-bit EEPROM with I2C-bus interface
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參數(shù)描述
PCA8565BS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Real time clock/calendar
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PCA8565TS 制造商:PHIL 功能描述:
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