參數(shù)資料
型號： PC8260MTPU150
廠商： Atmel Corp.
英文描述： PowerPC-based Communications Processors
中文描述： 基于PowerPC的通信處理器
文件頁數(shù)： 31/53頁
文件大小： 364K
代理商： PC8260MTPU150
31
PC8260PowerQUICCII
2131B–HIREL–02/03
TRIS
ThreeState
I
AssertingTRISforcesallotherPowerQUICCII’spinstohighimpedance
state.
PORESET
Power-onReset
I
Whenasserted,thisinputlinecausesthePowerQUICCIItoenter
power-onresetstate.
HRESET
HardReset
I/O
Thisopendrainline,whenasserted,causesthePowerQUICCIItoenter
hardresetstate.
SRESET
SoftReset
I/O
Thisopendrainline,whenasserted,causesthePowerQUICCIItoenter
softresetstate.
QREQ
QuiescentRequest
O
ThispinindicatesthatPowerQUICCII’sinternalcoreisabouttoenterits
lowpowermode.InthePowerQUICCII,thispinwillbetypicallyusedfor
debugpurposes.
RSTCONF
ResetConfiguration
I
ThisinputlienissampledbythePowerQUICCIIduringtheassertionof
theHRESETsignal.Ifthelineisasserted,theconfigurationmodeis
sampledintheformofthehardresetconfigurationworddrivenonthe
databus.Whenthislineisnegated,thedefaultconfigurationmodeis
adoptedbythePowerQUICCII.Noticethattheinitialbaseaddressof
internalregistersisdeterminedinthissequence.
MODCK1
AP[1]
TC[0]
BNKSEL[0]
ClockModeInput
I
Definestheoperatingmodeofinternalclockcircuits.
AddressParity1
I/O
The60xmasterthatdrivestheaddressbus,alsodrivestheaddress
paritysignals.Thevaluedrivenontheaddressparity1pinshould
provideoddparity(oddnumberof1’s)onthegroupofsignalsthat
includesaddressparity1and[A8:15].
TransferCode0
O
Thetransfercodeoutputpinssupplyinformationthatcanbeusefulfor
debugpurposesforeachofthePowerQUICCIIinitiatedbus
transactions.
BankSelect0
O
ThebankselectoutputsareusedforselectingSDRAMbankwhenthe
PowerQUICCIIisin60xcompatiblebusmode.
MODCK2
AP[2]
TC[1]
BNKSEL[1]
ClockModeInput
I
Definestheoperatingmodeofinternalclockcircuits.
AddressParity2
I/O
The60xmasterthatdrivestheaddressbus,alsodrivestheaddress
paritysignals.Thevaluedrivenontheaddressparity2pinshould
provideoddparity(oddnumberof1’s)onthegroupofsignalsthat
includesaddressparity2and[A16:23].
TransferCode1
O
Thetransfercodeoutputpinssupplyinformationthatcanbeusefulfor
debugpurposesforeachofthePowerQUICCIIinitiatedbus
transactions.
BankSelect1
O
ThebankselectoutputsareusedforselectingSDRAMbankwhenthe
PowerQUICCIIisin60xcompatiblebusmode.
Table4.
ExternalSignals(Continued)
Pin
SignalName
Type
Description
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