參數(shù)資料
型號： PC8260MTPU150
廠商： Atmel Corp.
英文描述： PowerPC-based Communications Processors
中文描述： 基于PowerPC的通信處理器
文件頁數(shù)： 25/53頁
文件大?。?/td> 364K
代理商： PC8260MTPU150
25
PC8260PowerQUICCII
2131B–HIREL–02/03
L2HIT
IRQ4
L2CacheHit
I
ThispinisusedforL2cachecontrol.Assertionofthispinindicatesthat
the60xtransactionwillbehandledbytheL2cache.Inthiscase,the
memorycontrollerwillnotstartanaccesstothememoryitcontrols.
InterruptRequest4
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
CPUBG
BADDR31
IRQ5
CPUBusGrant
O
Thevalueofthe60xcorebusgrantisdrivenonthispinforthe
BADDR31useofanexternalL2cache.Thedrivenbusgrantisnon
qualified.thatis,intheIRQ5caseofexternalarbiter,theusershould
qualifythissignalwiththebusgrantinputtothePowerQUICCIIbefore
connectingittotheL2Cache.
Burstaddress31
O
Therearefiveburstaddressoutputsofthe60xmemorycontrollerused
intheexternalmasterconfigurationandareconnecteddirectlytothe
memorydevicescontrolledbyPowerQUICCII’smemorycontroller.
InterruptRequest5
I
Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof
theinternalinterruptcontroller)aserviceroutinefromthecore.
CPUDBG
CPUBusDataBusGrant
O
Thevalueofthe60xcoredatabusgrantisdrivenonthispinfortheuse
ofanexternalL2cache.
CPUBR
CPUBusRequest
O
Thevalueofthe60xcorebusrequestisdrivenonthispinfortheuseof
anexternalL2cache.
CS[0:9]
ChipSelect
O
Theseareoutputpinsthatenablespecificmemorydevicesor
peripheralsconnectedtoPowerQUICCIIbuses.
CS[10]
BCTL1
DBGDIS
ChipSelect
O
Thisisanoutputpinthatenablesspecificmemorydevicesor
peripheralsconnectedtoPowerQUICCIIbuses.
BufferControl1
O
Outputsignalwhosefunctionistocontrolbuffersonthe60xdatabus.
ThispinwillusuallybeusedwithBCTL0.Theexactfunctionofthispinis
definedbythevalueofSIUMCR[BCTLC].See6.5.1.8SIUModule
ConfigurationRegisterfordetails.
DataBusGrantDisable
O
ThisisanoutputwhenthePowerQUICCIIisinexternalarbitermode
andaninputwhenthePowerQUICCIIisininternalarbitermode.When
thispinisasserted,the60xbusarbitershouldnegateallofitsDBG
outputstopreventdatabuscontention.
CS[11]
AP[0]
ChipSelect
O
Outputthatenablesspecificmemorydevicesorperipheralsconnected
toPowerQUICCIIbuses.
AddressParity0
I/O
The60xmasterthatdrivestheaddressbus,alsodrivestheaddress
paritysignals.Thevaluedrivenonaddressparity0pinshouldprovide
oddparity(oddnumberof1’s)onthegroupofsignalsthatincludes
addressparity0andA[0:7].
BADDR[27:28]
BurstAddress27:28
O
Therearefiveburstaddressoutputpins.Thesepinsareoutputsofthe
60xmemorycontroller.Usedinexternalmasterconfigurationand
connecteddirectlytothememorydevicescontrolledbyPowerQUICC
II’smemorycontroller.
ALE
AddressLatchEnable
O
Thisoutputpincontrolstheexternaladdresslatchthatshouldbeusedin
externalmaster60xbusconfiguration.
BCTLO
BufferControl0
AnOutputwhosefunctionistocontrolbuffersonthe60xdatabus.This
pinwillusuallybeusedwithBCTL1thatisMUXedonCS10.Theexact
functionofthispinisdefinedbythevalueofSIUMCR[BCTLC].See
6.5.1.8SIUModuleConfigurationRegisterfordetails.
Table4.
ExternalSignals(Continued)
Pin
SignalName
Type
Description
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