參數(shù)資料
型號(hào)： PC2119VU
廠商： NXP Semiconductors N.V.
英文描述： KPTC 23C 21#20 2#16 PIN PLUG
中文描述： LCD控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 7/60頁(yè)
文件大?。?/td> 260K
代理商： PC2119VU
1999 Mar 02
7
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
7.5
External clock
If an external clock is to be used this is input at the OSC
pad. The resulting display frame frequency is given by:
f
3072
Only in the power-down state is the clock allowed to be
stopped (OSC connected to V
SS
), otherwise the LCD is
frozen in a DC state.
7.6
Power-on reset
The PC2119x must be reset externally. This is an internal
synchronous reset that requires 3 OSC cycles to be
executed after release of the external reset signal. If no
external reset is performed, the chip might start-up in an
unwanted state. The external reset is active HIGH.
7.7
Power-down mode
The chip can be put into power-down mode where all static
currents are switched off (no internal oscillator, no bias
level generation and all LCD outputs are internally
connected to V
SS
) when PD = 1.
During power-down, information in the RAMs and the chip
state are preserved. Instruction execution during
power-down is possible when pad OSC is externally
clocked.
7.8
Registers
The PCF2119x has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed. The instruction register stores instruction codes
such as ‘display clear’ and ‘cursor shift’, and address
information for the Display Data RAM (DDRAM) and
Character Generator RAM (CGRAM).
The instruction register can be written to but not read from
by the system controller. The data register temporarily
stores data to be read from the DDRAM and CGRAM.
f
frame
-------------
=
When reading, data from the DDRAM or CGRAM
corresponding to the address in the instruction register is
written to the data register prior to being read by the ‘read
data’ instruction.
7.9
Busy flag
The busy flag indicates the internal status of the
PCF2119x. A logic 1 indicates that the chip is busy and
further instructions will not be accepted. The busy flag is
output to pad DB7 when RS = 0 and R/W = 1. Instructions
should only be written after checking that the busy flag is
at logic 0 or waiting for the required number of cycles.
7.10
Address Counter (AC)
The address counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
commands ‘set CGRAM address’ and ‘set DDRAM
address’. After a read/write operation the address counter
is automatically incremented or decremented by 1.
The address counter contents are output to the bus
(DB6 to DB0) when RS = 0 and R/W = 1.
7.11
Display Data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data
represented by 8-bit character codes. RAM locations
which are not used for storing display data can be used as
general purpose RAM. The basic RAM to display
addressing scheme is shown in Fig.2. With no display shift
the characters represented by the codes in the first
32 RAM locations starting at address 00H in line 1 are
displayed. Figures 3 and 4 show the display mapping for
right and left shift respectively.
When data is written to or read from the DDRAM
wrap-around occurs from the end of one line to the start of
the next line. When the display is shifted each line wraps
around within itself, independently of the others. Thus all
lines are shifted and wrapped around together.
The address ranges and wrap-around operations for the
various modes are shown in Table 3.
Table 3
Address space and wrap-around operation
MODE
1
×
32
00 to 4F
4F to 00
2
×
16
1
×
9
00 to 27
27 to 00
Address space
Read/write wrap-around (moves to
next line)
Display shift wrap-around (stays within
line)
00 to 27; 40 to 67
27 to 40; 67 to 00
Do not use (make sure, that 4F and 00
are not displayed at the same time.)
27 to 00; 67 to 40
27 to 00
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