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參數(shù)資料
| 型號： | PC107AVGHU100LD |
| 廠商： | ATMEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PCI Bridge Memory Controller |
| 中文描述： | MULTIFUNCTION PERIPHERAL, CBGA503 |
| 封裝： | 33 X 33 MM, HITCE, CERAMIC, BGA-503 |
| 文件頁數(shù)： | 9/50頁 |
| 文件大?。?/td> | 453K |
| 代理商： | PC107AVGHU100LD |
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9
PC107A [Preliminary]
2137C–HIREL–03/04
Notes:
1. This pin has an internal pull-up resistor which is enabled only when the PC107A is in the reset state. The value of the inter-
nal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic "1" is read into configuration bits during reset.
2. This pin is a reset configuration pin.
3. MDL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC107 is in the
reset state.The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a logic '1' is read into
configuration bits during reset.
4. Multi-pin signals such as AD[0–31] or DL[0–31] have their physical package pin numbers listed in order corresponding to the
signal names. Ex: AD0 is on pin D21, AD1 is on pin D23,... AD31 is on pin N23.
5. SDMA[10–1] are reset configuration pins and have internal pull-up resistors which are enabled only when the MPC107 is in
the reset state.The values of the internal pull-up resistors is not guaranteed, but are sufficient to ensure that logic "1"s are
read into the configuration bits during reset.
6. Recommend a weak pull-up resistor (2 k
– 10 k
) be placed on this PCI control pin to LV
DD
.
7. V
IH
and V
IL
for these signals are the same as the PCI V
IH
and V
IL
entries in Table 7, “DC Electrical Specifications.”
8. Recommend a weak pull-up resistor (2 k
– 10 k
) be placed on this pin to OV
DD
.
9. Recommend a weak pull-up resistor (2 k
– 10 k
) be placed on this pin to GV
DD
.
10. This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent
unused inputs from floating.
11. This pin is affected by programmable PCI_HOLD_DEL parameter, see “PCI Signal Output Hold Timing” on page 29.”
12. This pin is an open drain signal.
13. This pin is a sustained tri-state pin as defined by the
PCI Local Bus Specification.
14. See “Connection Recommendations” on page 43 for additional information on this pin.
15. A weak pull-up resistor is recommend (2 k
– 10 k
) to be placed on this pin to BV
DD
.
16. If BV
DD
= 2.5V
±
5%, this microprocessor interface pin needs to be DC voltage level shifted from OV
DD
(3.3
±
0.3V) to 2.5V
±
5%; this can typically be accomplished with a two resistor voltage divider circuit since the signal is an output only signal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC107AVZFU100L | PCI Bridge Memory Controller |
| PC107AVZFU100LC | PCI Bridge Memory Controller |
| PC107AVZFU100LD | PCI Bridge Memory Controller |
| PC107AVGHU100L | PCI Bridge Memory Controller |
| PC107A | PCI Bridge Memory Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC107AVZFU100L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AVZFU100LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AVZFU100LD | 制造商:e2v technologies 功能描述:IC BRIDGE MEM CTRL 100 MHZ - Trays |
| PC107B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| PC107C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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