參數(shù)資料
型號： PC107AVGHU100L
廠商： Atmel Corp.
英文描述： PCI Bridge Memory Controller
中文描述： PCI橋內(nèi)存控制器
文件頁數(shù)： 28/50頁
文件大小： 453K
代理商： PC107AVGHU100L
28
PC107A [Preliminary]
2137C–HIREL–03/04
Output AC Timing
Specification
Table 12 provides the processor bus AC timing specifications for the PC107A. See Fig-
ure 13 on page 27 and Figure 14 on page 27.
At recommended operating conditions (see Table 3 on page 12) with
LV
DD
= 3.3
±
0.3V
Notes:
1. All memory and related interface output signal specifications are specified from the V
M
= 1.4V of the rising edge of the mem-
ory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on
every rising and falling edge of PCI_SYNC_IN). See Figure 13 on page 27.
2. All PCI signals are measured from OV
DD
/2 of the rising edge of PCI_SYNC_IN to 0.285*OV
DD
or 0.615*OV
DD
of the signal in
question for 3.3V PCI signaling levels. See Figure 14 on page 27.
3. All output timings assume a purely resistive 50
load (See Figure 16 on page 28). Output timings are measured at the pin;
time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
4. PCI Bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0–3], PAR, TRDY, FRAME, STOP, DEVSEL,
PERR, SERR, AD[0–31], REQ[4–0], GNT[4–0], IDSEL, INTA.
5. PCI hold times can be varied, see “PCI Signal Output Hold Timing” on page 29 for information on programmable PCI output
hold times. The values shown for item 13a are for PCI compliance.
6. These specifications are for the default driver strengths indicated in Table 8 on page 22.
Figure 16.
AC Test Load for the PC107A
Table 12.
Output AC Timing Specifications
Num
Characteristics
(3)(6)
Min
Max
Unit
Notes
12a
PCI_SYNC_IN to Output Valid, 66 MHz PCI, with SDMA4 pulled-
down to logic 0 state. See Figure 17.
–
6.0
ns
(2)(4)
PCI_SYNC_IN to Output Valid, 33 MHz PCI, with SDMA4 in the
default logic 1 state. See Figure 17.
–
11.0
ns
(2)(4)
12b
Memory Interface Signals, SDRAM_SYNC_IN to Output Valid
–
5.5
ns
(1)
12b1
Memory Interface Signal: CKE (100 MHz Device),
SDRAM_SYNC_IN to Output Valid
–
5.5
ns
(1)
12b2
Memory Interface Signal: CKE (66 MHz Device),
SDRAM_SYNC_IN to Output Valid
–
6.0
ns
(1)
12c
Epic, Misc. Debug Signals, SDRAM_SYNC_IN to Output Valid
–
9.0
ns
(1)
12d
Two-wire interface, SDRAM_SYNC_IN to Output Valid
–
5.0
ns
(1)
12e
60x Processor Interface Signals, SDRAM_SYNC_IN to Output Valid
–
5.5
ns
(1)
13a
Output Hold, 66 MHz PCI, with SDMA4 and SDMA3 pulled-down to
logic 0 states. See Table 13.
1.0
–
ns
(2)(4)(5)
Output Hold, 33 MHz PCI, with SDMA4 in the default logic 1 state
and SDMA3 pulled-down to logic 0 state. See Table 13.
2.0
–
ns
(2)(4)(5)
13b
Output Hold (For All Others)
1
ns
(1)
14a
PCI_SYNC_IN to Output High Impedance (T
off
for PCI)
–
14.0
ns
(2)(4)
14b
SDRAM_SYNC_IN to Output High Impedance (For All Others)
–
4.0
ns
(1)
OUTPUT
Z0 = 50
OVdd/2
RL = 50
PIN
Output measurements are made at the device pin.
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