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參數(shù)資料
| 型號(hào)： | P8C15416Y-12 |
| 英文描述： | IC-8-BIT CMOS CPU |
| 中文描述： | 集成電路8位CMOS處理器 |
| 文件頁數(shù)： | 19/25頁 |
| 文件大小： | 154K |
| 代理商： | P8C15416Y-12 |
80C32/80C52
19
Rev. I
–
September 18, 1998
8.7. AC Parameters
TA= 0 to + 70
°
C; VSS= 0 V; VCC= 5 V
±
10 %; F= 0 to 44 MHz
TA= 0 to +70
°
C; VSS= 0 V; 2.7 V < VCC < 5.5 V; F= 0 to 16 MHz
TA= –40
°
to + 85
°
C; VSS= 0 V; 2.7 V < VCC < 5.5 V; F= 0 to 16 MHz
TA= –55
°
+ 125
°
C; VSS= 0 V; VCC= 5 V
±
10 %; F= 0 to 36 MHz
(Load Capacitance for PORT 0, ALE and PSEN= 100 pF; Load Capacitance for all other outputs= 80 pF)
Table 8. External Program Memory Characteristics (values in ns)
16 MHz
20 MHz
25 MHz
30 MHz
36 MHz
40 MHz
42 MHz
44 MHz
Symbol
Parameter
min max min max min max min max min max min max min max min max
TLHLL
ALE Pulse Width
110
90
70
60
50
40
35
30
TAVLL
Address valid to ALE
40
30
20
15
10
9
8
7
TLLAX
Address Hold After ALE
35
35
35
35
35
30
25
17
TLLIV
ALE to valid instr in
185
170
130
100
80
70
65
65
TLLPL
ALE to PSEN
45
40
30
25
20
15
13
12
TPLPH
PSEN pulse Width
165
130
100
80
75
65
60
54
TPLIV
PSEN to valid instr in
125
110
85
65
50
45
40
35
TPXIX
Input instr Hold After PSEN
0
0
0
0
0
0
0
0
TPXIZ
Input instr Float After PSEN
50
45
35
30
25
20
15
10
TPXAV
PSEN to Address Valid
55
50
40
35
30
25
20
15
TAVIV
Address to Valid instr in
230
210
170
130
90
80
75
70
TPLAZ
PSEN low to Address Float
10
10
8
6
5
5
5
5
TPLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0–A7
A0–A7
INSTR IN
INSTR IN
INSTR IN
ADDRESS
OR SFR–P2
ADDRESS A8–A15
ADDRESS A8–A15
12 TCLCL
TAVIV
TLHLL
TAVLL
TLLIV
TLLPL
TPLPH
TPXAV
TPXIX
TPXIZ
TLLAX
Figure 13. External Program Memory Read Cycle
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