參數(shù)資料
型號(hào)： P8C15416Y-12
英文描述： IC-8-BIT CMOS CPU
中文描述： 集成電路8位CMOS處理器
文件頁(yè)數(shù)： 11/25頁(yè)
文件大小： 154K
代理商： P8C15416Y-12
80C32/80C52
11
Rev. I
–
September 18, 1998
T2CON (S:C8h)
Timer/Counter 2 Control Register
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
Mnemonic
Description
7
TF2
Timer 2 Overflow flag
TF2 is not set if RCLK= 1 or TCLK= 1.
Set by hardware when Timer 2 overflows.
Must be cleared by software
6
EXF2
Timer 2 External flag
EXF2 does not cause an interrupt in up/down counter mode (DCEN= 1).
Set by hardware if EXEN2= 1 when a negative transition on T2EX pin is detected.
5
RCLK
Receive Clock bit
Clear to select Timer 1 as the Timer Receive Baud Rate Generator for the Serial Port in modes 1 and 3.
Set to select Timer 2 as the Timer Receive Baud Rate Generator for the Serial Port in modes 1 and 3.
4
TCLK
Transmit Clock bit
Clear to select Timer 1 as the Timer Transmit Baud Rate Generator for the Serial Port in modes 1 and 3.
Set to select Timer 2 as the Timer Transmit Baud Rate Generator for the Serial Port in modes 1 and 3.
3
EXEN2
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for Timer 2.
Set to cause a capture or reload when a negative transition on T2EX pin is detected unless Timer 2 is being
used as the Baud Rate Generator for the Serial Port.
2
TR2
Timer 2 Run Control bit
Clear to turn off Timer 2.
Set to to turn on Timer 2.
1
C/T2#
Timer 2 Counter/Timer Select bit
Clear for Timer operation: Timer 2 counts the divided–down system clock.
Set for Counter operation: Timer 2 counts negative transitions on external pin T2.
0
CP/RL2#
Capture/Reload bit
CP/RL2
#
is ignored and Timer 2 is forced to auto–reload on Timer 2 overflow if RCLK= 1 or TCLK= 1.
Clear to auto–reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2= 1.
Set to capture on negative transitions on T2EX pin if EXEN2= 1
Reset Value= 0000 0000b
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