參數(shù)資料
型號(hào)： P8C15416Y-12
英文描述： IC-8-BIT CMOS CPU
中文描述： 集成電路8位CMOS處理器
文件頁(yè)數(shù)： 16/25頁(yè)
文件大小： 154K
代理商： P8C15416Y-12
80C32/80C52
16
Rev. I
–
September 18, 1998
8.5. DC parameters – Low voltage – Commercial and Industrial
Table 6. DC Characteristics
TA= 0
°
C to 70
°
C; VCC= 2.7 V to 5.5 V; VSS= 0 V; F= 0 to 16 MHz
TA= –40
°
C to 85
°
C; VCC= 2.7 V to 5.5 V
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIL
Input Low Voltage
– 0.5
0.2 VCC – 0.1
V
VIH
Input High Voltage (Except XTAL and RST)
0.2 VCC + 1.4
VCC
+ 0.5
V
VIH2
Input High Voltage to RST for Reset
0.7 VCC
VCC + 0.5
V
VIH1
Input High Voltage to XTAL1
0.7 VCC
VCC + 0.5
V
VPD
Power Down Voltage to VCC in PD Mode
2.0
5.5
V
VOL
Output Low Voltage (Ports 1, 2, 3)
0.45
V
IOL= 0.8 mA
(4)
VOL1
Output Low Voltage Port 0, ALE, PSEN
0.45
V
IOL= 1.6 mA
(4)
VOH
Output High Voltage Ports 1, 2, 3
0.9 VCC
V
IOH= – 10
μ
A
VOH1
Output High Voltage (Port 0 in External Bus
Mode), ALE, PSEN
0.9 VCC
V
IOH= – 40
μ
A
IIL
Logical 0 Input Current Ports 1, 2, 3
– 50
μ
A
Vin= 0.45 V
ILI
Input Leakage Current
±
10
μ
A
0.45 < Vin < VCC
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
– 650
μ
A
Vin= 2.0 V
IPD
Power Down Current
50
μ
A
VCC= 2.0 V to 5.5 V
(3)
RRST
RST Pulldown Resistor
50
200
k
CIO
Capacitance of I/O Buffer
10
pF
MHz, T
A
= 25 C
Notes:
1.
ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + .5 V, VIH= VCC –.5 V; XTAL2
N.C. ; EA = RST = Port 0 = VCC. ICC would be slighty higher if a crystal oscillator used.
Idle ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL= 5 ns, VIL= VSS + 5 V, VIH= VCC –.5 V ;
XTAL2 N.C; Port 0= VCC; EA= RST= VSS.
Power Down ICC is measured with all output pins disconnected; EA= PORT 0= VCC; XTAL2 N.C. ; RST= VSS.
Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The
noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus
operations. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45 V may exceed 0,45 V with maxi
VOL peak 0.6 V. A Schmitt Trigger use is not necessary.
2.
3.
4.
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