參數(shù)資料
型號(hào)： P89V52X2FN,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 33/57頁(yè)
文件大小： 0K
描述： IC 80C51 MCU FLASH 8K 40-DIP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 216
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設(shè)備： POR
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 192 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1012-ND - BOARD FOR P89V52X2 44-TQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
其它名稱： 568-4251-5
935282526112
P89V52X2FN
P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
39 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
FMDATA = dbytes[i];
}
FMCON = EP;//erase & prog page command
Fm_stat = FMCON;//read the result status
if ((Fm_stat & 0x0F)!=0) prog_fail=1; else prog_fail=0;
return(prog_fail);
}
6.13.7 Data EEPROM write enable
The data EEPROM has a Write Enable mechanism to help prevent against inadvertent
writes. If the WE bit (FMCON.6) is set writes to the data EEPROM are enabled. When
cleared, writes are disabled. This bit only affects execution mode. The WE bit is set when:
The disable write enable bit, DISWE (UCFG.2) = 1
In ICP mode
The SET_WE (08H) command is written to FMCON followed by the key value (96H)
being written to FMDATA
The WE bit is cleared following any reset. The WE bit may also be cleared by writing the
CLR_WE (0BH) command to FMCON.
6.13.8 Data EEPROM security bits
The data EEPROM security bits protects each data EEPROM page. The data EEPROM
page security bits and their effects are shown in Table 35.
6.13.9 Summary of data EEPROM commands
Table 37 is a summary of the FMCON commands related to the data EEPROM.
Table 35.
DPxSEC - Data page X security register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
XERSx
PWRx
MOVCx
Table 36.
DPxSEC - Data page X security register bit description
Bit
Symbol
Description
7 to 3
-
Reserved
2
XERSx
Execution Erase Protect x. When programmed = 1, cannot be erased
with ERS_DP command in execution mode. ERS_DP can be used in
ICP mode.
1
PWRx
Page Write Protect x. When programmed = 1, data EEPROM cannot
be erased or programmed using PROG or EP commands.
0
MOVCx
When programmed = 1, prevents instructions fetched from off-chip
from reading the contents of the data EEPROM and returns FFH.
CRC_DP are disabled if the corresponding Page Write Protect is
disabled.
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