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| 型號(hào)： | P89V52X2FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 21/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 40-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 216 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON |
| 其它名稱： | 568-4251-5 935282526112 P89V52X2FN |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
28 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the nal shift pulse is generated: (a) RI = 0, and
(b) Either SM2 = 0, or the received 9th data bit = 1.
If either of these conditions is not met, the received frame is irretrievably lost, and RI is not
set. If both conditions are met, the received 9th data bit goes into RB8, and the rst 8 data
bits go into SBUF.
6.10.8 Multiprocessor communications
UART modes 2 and 3 have a special provision for multiprocessor communications. In
these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is
stored in RB8. The UART can be programmed so that when the stop bit is received, the
serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit
SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:
When the master processor wants to transmit a block of data to one of several slaves, it
rst sends out an address byte which identies the target slave. An address byte differs
from a data byte in a way that the 9th bit is ‘1’ in an address byte and ‘0’ in the data byte.
With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is ‘0’.
However, an address byte having the 9th bit set to ‘1’ will interrupt all slaves, so that each
slave can examine the received byte and see if it is being addressed or not. The
addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that
follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about
their business, ignoring the subsequent data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop
bit, although this is better done with the Framing Error ag. When UART receives data in
mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is
received.
6.10.9 Automatic address recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain
addresses in the serial bit stream by using hardware to make the comparisons. This
feature saves a great deal of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This feature is enabled for
the UART by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3,
the Receive Interrupt ag (RI) will be automatically set when the received byte contains
either the ‘Given’ address or the ‘Broadcast' address. The 9 bit mode requires that the 9th
information bit is a ‘1’ to indicate that the received information is an address and not data.
Using the Automatic Address Recognition feature allows a master to selectively
communicate with one or more slaves by invoking the Given slave address or addresses.
All of the slaves may be contacted by using the Broadcast address. Two Special Function
Registers are used to dene the slave’s address, SADDR, and the address mask,
SADEN. SADEN is used to dene which bits in the SADDR are to be used and which bits
are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the
‘Given’ address which the master will use for addressing each of the slaves. Use of the
Given address allows multiple slaves to be recognized while excluding others.
This device uses the methods presented in Figure 18 to determine if a ‘Given’ or
‘Broadcast’ address has been received or not.
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| P89V660 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660_0811 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
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