參數(shù)資料
型號(hào)： P89V52X2FN,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 24/57頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 8K 40-DIP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 216
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設(shè)備： POR
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 192 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1012-ND - BOARD FOR P89V52X2 44-TQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
其它名稱(chēng)： 568-4251-5
935282526112
P89V52X2FN
P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
30 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
(6)
Example 2, slave 1:
(7)
Example 2, slave 2:
(8)
In the above example the differentiation among the 3 slaves is in the lower 3 address bits.
Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1
requires that bit1=0 and it can be uniquely addressed by 1110 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude
Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and
SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the
don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR
and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well
as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic
Addressing mode and allows the microcontroller to use standard UART drivers which do
not make use of this feature.
6.11 Interrupt priority and polling sequence
The device supports six interrupt sources under a four level priority scheme. Table 24
summarizes the polling sequence of the supported interrupts. (See Figure 19).
SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
----------------------------------------------------
SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
----------------------------------------------------
SADDR = 1100 0000
SADEN = 1111 1100
Given = 1100 00XX
----------------------------------------------------
Table 24.
Interrupt polling sequence
Description
Interrupt ag
Vector address Interrupt
enable
Interrupt
priority
Service
priority
Wake-up
Power-down
External
Interrupt 0
IE0
0003H
EX0
PX0/H
1 (highest)
yes
T0
TF0
000BH
ET0
PT0/H
2
no
External
Interrupt 1
IE1
0013H
EX1
PX1/H
3
yes
T1
TF1
001BH
ET1
PT1/H
4
no
UART
TI/RI
0023H
ES0
PS0/H
5
no
T2
TF2, EXF2
003BH
ET2
PT2/H
6
no
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