參數(shù)資料
型號(hào): P89LPC952FBD,157
廠商: NXP Semiconductors
文件頁數(shù): 39/69頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 44-LQFD
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1016-ND - BOARD FOR P89LPC952FA 44-PLCC
622-1008-ND - BOARD FOR LPC9103 10-HVSON
OM10075-ND - EVAL BOARD FOR LPC952
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-2014-5
935280152157
P89LPC952FBD
P89LPC952FDH-S
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
44 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.26 Flash program memory
7.26.1 General description
The P89LPC952/954 ash memory provides in-circuit electrical erasure and
programming. The ash can be erased, read, and written as bytes. The Sector and Page
Erase functions can erase any ash sector (1 kB) or page (64 bytes). The Chip Erase
operation will erase the entire program memory. ICP using standard commercial
programmers is available. In addition, IAP and byte-erase allows code memory to be used
for non-volatile data storage. On-chip erase and write timing generation contribute to a
user-friendly programming interface. The P89LPC952/954 ash reliably stores memory
contents even after 400,000 erase and program cycles. The cell is designed to optimize
the erase and programming mechanisms. The P89LPC952/954 uses VDD as the supply
voltage to perform the Program/Erase algorithms.
7.26.2 Features
Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP, IAP, ICP, or two-wire serial debugger.
Internal xed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program
memory.
Boot vector allows user-provided ash loader code to reside anywhere in the ash
memory space, providing exibility to the user.
Any ash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the ash for each sector.
400,000 typical erase/program cycles for each byte.
20 year minimum data retention.
7.26.3 Flash organization
The program memory consists of eight/sixteen 1 kB sectors on the P89LPC952/954
devices. Each sector can be further divided into 64-byte pages. In addition to sector
erase, page erase, and byte erase, a 64-byte page register is included which allows from
1 to 64 bytes of a given page to be programmed at the same time, substantially reducing
overall programming time.
7.26.4 Using ash as data storage
The ash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a MOVC
instruction is not allowed to read code memory contents of a secured sector). Thus any
byte in a non-secured sector may be used for non-volatile data storage.
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