參數(shù)資料
型號: P89LPC952FBD,157
廠商: NXP Semiconductors
文件頁數(shù): 12/69頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 44-LQFD
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1016-ND - BOARD FOR P89LPC952FA 44-PLCC
622-1008-ND - BOARD FOR LPC9103 10-HVSON
OM10075-ND - EVAL BOARD FOR LPC952
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-2014-5
935280152157
P89LPC952FBD
P89LPC952FDH-S
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
2 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
2.2 Additional features
I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
I Serial ash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
I Serial ash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
I In-Application Programming (IAP) of the ash code memory. This allows changing the
code in a running application.
I Low voltage (brownout) detect allows a graceful system shutdown when power fails.
May optionally be congured as an interrupt.
I Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1
A (total power-down with voltage comparators disabled).
I On-chip power-on reset allows operation without external reset components. A
software reset function is also available.
I Programmable external reset pin (P1.5) conguration options: open drain bidirectional
reset input/output, reset input with pull-up, push-pull reset output, input-only port. A
reset counter and reset glitch suppression circuitry prevent spurious and incomplete
resets.
I Only power and ground connections are required to operate the P89LPC952/954
when internal reset option is selected.
I Congurable on-chip oscillator with frequency range options selected by user
programmed ash conguration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
I Programmable port output conguration options: quasi-bidirectional, open drain,
push-pull, input-only.
I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
I Four interrupt priority levels.
I Eight keypad interrupt inputs, plus two additional external interrupt inputs.
I Schmitt trigger port inputs.
I Second data pointer.
I Extended temperature range.
I Emulation support.
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