參數(shù)資料
型號(hào): P89LPC9103FTK,115
廠商: NXP Semiconductors
文件頁(yè)數(shù): 5/39頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 1K 10-HVSON
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 1
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲(chǔ)器容量: 1KB(1K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-VFDFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
配用: 622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
622-1004-ND - BOARD DEMO FOR PHILIPS PCA9633
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-2001-6
P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
13 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
P1.5/RST
2
I
P1.5 — Port 1 bit 5 (input-only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specied level.
When system power is removed VDD will fall below the minimum specied
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specied operating voltage.
VSS
3I
Ground: 0 V reference.
VDD
7I
Power supply: This is the power supply voltage for normal operation as well as Idle
mode and Power-down mode.
Table 5.
P89LPC9103 pin description …continued
Symbol
Pin
Type
Description
Table 6.
P89LPC9107 pin description
Symbol
Pin
Type
Description
P0.1 to P0.5,
P0.7
I/O
Port 0: Port 0 is an I/O port with a user-congurable output type. During reset Port 0
latches are congured in the input-only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port conguration
selected. Each port pin is congured independently. Refer to Section 8.12.1 “Port
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.1/KBI1/
AD10
5
I/O
P0.1 — Port 0 bit 1.
I
KBI1 — Keyboard input 1.
I
AD10 — ADC1 channel 0 analog input.
P0.2/KBI2/
AD11
1
I/O
P0.2 — Port 0 bit 2.
I
KBI2 — Keyboard input 2.
I
AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/
AD12
14
I/O
P0.3 — Port 0 bit 3.
I
CIN1B — Comparator 1 positive input.
I
AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/
AD13/DAC1
12
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input.
I
AD13 — ADC1 channel 3 analog input.
O
DAC1 — Digital to analog converter output.
P0.5/CMPREF/
CLKIN
11
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
CLKIN — External clock input.
P0.7/T1/
CLKOUT
8
I/O
P0.7 — Port 0 bit 7.
I/O
T1 — Timer/counter 1 external count input or overow/PWM output.
I
CLKOUT — Clock output.
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