參數(shù)資料
型號: P89CV51RD2FBC,557
廠商: NXP Semiconductors
文件頁數(shù): 55/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 64K 44-TQFP
產品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 800
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
其它名稱: 568-4257
935284103557
P89CV51RD2FBC
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
59 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
7.
Limiting values
8.
Static characteristics
Table 53.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Parameters are valid over operating temperature
range unless otherwise specied; all voltages are with respect to VSS unless otherwise noted.
Symbol
Parameter
Conditions
Min
Max
Unit
Tamb(bias)
bias ambient temperature
55
+125
°C
Tstg
storage temperature
65
+150
°C
VI
input voltage
on EA pin to VSS
0.5
+14
V
Vn
voltage on any other pin
except VSS; with respect to
VDD
0.5
VDD + 0.5
V
IOL(I/O)
LOW-level output current per
input/output pin
-15
mA
Ptot(pack)
total power dissipation (per package)
based on package heat
transfer, not device power
consumption
-
1.5
W
Table 54.
Static characteristics
Tamb = 40 °C to +85 °C; VDD = 4.5 V to 5.5 V; VSS =0V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
nendu()
endurance of ash memory
JEDEC Standard A117
[1] 10000
-
cycles
tret()
ash memory retention time JEDEC Standard A103
[1] 100
-
years
Ilatch
I/O latch-up current
JEDEC Standard 78
[1] 100 + IDD
--
mA
Vth(HL)
HIGH-LOW threshold
voltage
0.5
-
+0.2VDD 0.1
V
Vth(LH)
LOW-HIGH threshold
voltage
except XTAL1, RST
0.2VDD + 0.9 -
VDD + 0.5
V
VOL
LOW-level output voltage
VDD = 4.5 V;
except PSEN, ALE
IOL = 1.6 mA
-
0.4
V
VDD = 4.5 V; ALE, PSEN
IOL = 3.2 mA
-
0.45
V
VOH
HIGH-level output voltage
VDD = 4.5 V;
ports 1, 2, 3, 4
IOH = 30 AVDD 0.7
-
V
VDD = 4.5 V; port 0 in
External bus mode, ALE,
PSEN
IOH = 3.2 mA
VDD 0.7
-
V
IIL
LOW-level input current
VI = 0.4 V; ports 1, 2, 3, 4
1-
75
A
ITHL
HIGH-LOW transition
current
VI = 2 V; ports 1, 2, 3, 4
650
A
ILI
input leakage current
0.45 V < VI <VDD 0.3 V;
port 0
--
±10
A
0V<VI <6V
-
10
A
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