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參數(shù)資料
| 型號： | P89CV51RD2FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 20/76頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 其它名稱： | 568-4257 935284103557 P89CV51RD2FBC |
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P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
27 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the special function
register TMOD. These two timers/counters have four operating modes, which are selected
by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both timers/counters.
Mode 3 is different. The four operating modes are described in the following text.
Table 13.
TMOD - Timer/Counter mode control register (address 89H) bit allocation
Not bit addressable; reset value: 0000 0000B; reset source(s): any source.
Bit
7
6
5
4
3
2
1
0
Symbol
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
Table 14.
TMOD - Timer/Counter mode control register (address 89H) bit description
Bit
Symbol
Description
7
T1GATE
Gating control for Timer 1. When set, timer/counter is enabled only while
the INT1 pin is HIGH and the TR1 control bit is set. When cleared, Timer 1
is enabled when the TR1 control bit is set.
6
T1C/T
Timer or counter select for Timer 1. Cleared for timer operation. Set for
counter operation (input from T1 input pin).
5
T1M1
Mode select for Timer 1.
4
T1M0
3
T0GATE
Gating control for Timer 0. When set, timer/counter is enabled only while
the INT0 pin is HIGH and the TR0 control bit is set. When cleared, Timer 0
is enabled when the TR0 control bit is set.
2
T0C/T
Timer or counter select for Timer 0. Cleared for timer operation. Set for
counter operation (input from T0 input pin).
1
T0M1
Mode select for Timer 0.
0
T0M0
Table 15.
TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating
mode
M1
M0
Operating mode
0
8048 timer ‘TLx’ serves as 5-bit prescaler.
0
1
16-bit timer/counter ‘THx’ and ‘TLx' are cascaded;
there is no prescaler.
1
0
2
8-bit auto-reload timer/counter ‘THx’ holds a value
which is to be reloaded into ‘TLx’ each time it overows.
1
3
(Timer 0) TL0 is an 8-bit timer/counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only
controlled by Timer 1 control bits.
1
3
(Timer 1) timer/counter 1 stopped.
Table 16.
TCON - Timer/Counter control register (address 88H) bit allocation
Bit addressable; reset value: 0000 0000B; reset source(s): any reset.
Bit
7
6
5
4
3
2
1
0
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
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