參數(shù)資料
型號(hào)： P89CV51RD2FBC,557
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 30/76頁(yè)
文件大小： 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
其它名稱： 568-4257
935284103557
P89CV51RD2FBC
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
36 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.6 UART
The UART operates in all standard modes. Enhancements over the standard 80C51
UART include framing error detection, and automatic address recognition.
6.6.1 Mode 0
Serial data enters and exits through RXD, and TXD outputs the shift clock. Only 8 bits are
transmitted or received, LSB rst. The baud rate is xed at 1
6 of the CPU clock frequency.
The UART congured to operate in this mode outputs serial clock on the TXD line no
matter whether it sends or receives data on the RXD line.
6.6.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB rst), and a stop bit (logical 1). When data is received, the stop bit is stored
in RB8 in special function register SCON. The baud rate is variable and is determined by
the Timer 1/Timer 2 overow rate.
6.6.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8
data bits (LSB rst), a programmable 9th data bit, and a stop bit (logical 1). When data is
transmitted, the 9th data bit (TB8 in special function register SCON) can be assigned the
value of 0 or (e.g. the parity bit (P in special function register PSW) could be moved into
bit TB8). When data is received, the 9th data bit goes into RB8 in special function register
SCON, while the stop bit is ignored. The baud rate is programmable to either 1
16 or
1
32 of
the CPU clock frequency, as determined by the SMOD1 bit in PCON.
6.6.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB rst), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3
is the same as Mode 2 in all respects except baud rate. The baud rate in mode 3 is
variable and is determined by the Timer 1/Timer 2 overow rate.
Table 23.
Timer 2-generated commonly used baud rates
Rate
Oscillator frequency
Timer 2
RCAP2H
RCAP2L
750 kBd
12 MHz
FF
19.2 kBd
12 MHz
FF
D9
9.6 kBd
12 MHz
FF
B2
4.8 kBd
12 MHz
FF
64
2.4 kBd
12 MHz
FE
C8
600 Bd
12 MHz
FB
1E
220 Bd
12 MHz
F2
AF
600 Bd
6 MHz
FD
8F
220 Bd
6 MHz
F9
57
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