參數(shù)資料
型號: P89CV51RB2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 54/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44-PLCC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 1,300
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
其它名稱: 568-4252-5
935284111512
P89CV51RB2FA
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
58 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.13.1.1
Clock control register (CKCON)
By default, the device runs at twelve clock cycles per machine cycle (12-clock mode). The
device may be run at 6 clock cycles per machine cycle (6-clock mode) by programming of
either a non-volatile bit (FX2) or an SFR bit (X2); see Table 52 “Clock modes”. If the FX2
non-volatile bit is programmed, the device will run in 6-clock mode and the X2 SFR bit has
no effect. If the FX2 bit is erased, then the clock mode is controlled by the X2 SFR bit.
Table 50.
CKCON - Clock control register (address 8FH) bit allocation
Not bit addressable; reset value 00H.
Bit
7
6
5
4
3
2
1
0
Symbol
SPIX2
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Table 51.
CKCON - Clock control register (address 8FH) bit description
Bit
Symbol
Description
7
SPIX2
SPI clock; 0 = 6 clock cycles for each SPI clock cycle;
1 = 12 clock cycles
6
WDX2
Watchdog clock; 0 = 6 clock cycles for each WDT clock cycle;
1 = 12 clock cycles
5
PCAX2
PCA clock; 0 = 6 clock cycles for each PCA clock cycle;
1 = 12 clock cycles
4
SIX2
UART clock; 0 = 6 clock cycles for each UART clock cycle;
1 = 12 clock cycles
3
T2X2
Timer 2 clock; 0 = 6 clock cycles for each Timer 2 clock cycle;
1 = 12 clock cycles
2
T1X2
Timer 1 clock; 0 = 6 clock cycles for each Timer 1 clock cycle;
1 = 12 clock cycles
1
T0X2
Timer 0 clock; 0 = 6 clock cycles for each Timer 0 clock cycle;
1 = 12 clock cycles
0
X2
CPU clock; 0 = 12 clock cycles for each machine cycle;
1 = 6 clock cycles
Table 52.
Clock modes
FX2 clock mode bit
X2 bit
CPU clock mode
Peripheral clock
mode bit (e.g. T0X2)
Mode
erased
0
12-clock (default)
X
12-clock (default)
1
6-clock
0
6-clock
1
12-clock
programmed
X
6-clock
0
6-clock
1
12-clock
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