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參數(shù)資料
| 型號： | P89CV51RB2FA,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 10/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 16K 44-PLCC |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 1,300 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 其它名稱： | 568-4252-5 935284111512 P89CV51RB2FA |
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P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
18 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
Programming with industry-standard commercial programmers.
10000 typical erase/program cycles for each byte.
100 year minimum data retention.
6.3.3 Boot block
When the microcontroller programs its own ash memory, all of the low-level details are
handled by code (bootloader) that is contained in a boot block. A user program calls the
common entry point in the boot block with appropriate parameters to accomplish the
desired operation. Boot block operations include erase user code, program user code,
program security bits, chip erase, etc. The boot block logically overlays the program
memory space from FC00H to FFFFH, when it is enabled. The boot block may be
disabled on-the-y so that the upper 1 kB of user code is available to the user’s program.
6.3.4 Power-on reset code execution
The P89CV51RB2/RC2/RD2 contains two special ash elements: the boot vector and the
boot status bit. Following reset, the P89CV51RB2/RC2/RD2 examines the contents of the
boot status bit. If the boot status bit is set to zero, power-up execution starts at location
0000H, which is the normal start address of the user’s application code. When the boot
status bit is set to a value other than zero, the contents of the boot vector are used as the
high byte of the execution address and the low byte is set to 00H.
Table 10 shows the factory default boot vector setting for this device. A factory-provided
bootloader is pre-programmed into the address space indicated and uses the indicated
bootloader entry point to perform ISP functions.
6.3.5 Hardware activation of the bootloader
The bootloader can also be executed by forcing the device into ISP mode during a
power-on sequence. This has the same effect as having a non-zero status byte. This
allows an application to be built that will normally execute user code but can be manually
forced into ISP operation. This occurs by holding PSEN LOW at the falling edge of reset. If
the factory default setting for the boot vector (FCH) is changed, it will no longer point to the
factory pre-programmed ISP bootloader code. After programming the ash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
6.3.6 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal rmware to
facilitate remote programming of the P89CV51RB2/RC2/RD2 through the serial port. This
rmware is provided by NXP and embedded within each P89CV51RB2/RC2/RD2 device.
The NXP ISP facility has made in-circuit programming in an embedded application
possible with a minimum of additional expense in components and circuit board area. The
ISP function uses ve pins (VDD, VSS, TXD, RXD, and RST). Only a small connector
needs to be available to interface your application to an external circuit in order to use this
feature.
Table 10.
Default boot vector values and ISP entry points
Device
Default boot vector
Default bootloader entry point
Default bootloader code range
P89CV51RB2/RC2/RD2
FCH
FC00H
FC00H to FFFFH
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| P89CV51RB2FBC | 功能描述:8位微控制器 -MCU 80C51 16K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89CV51RB2FBC,557 | 功能描述:8位微控制器 -MCU 80C51 16K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89CV51RC2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 64 kB flash microcontroller with 1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals |
| P89CV51RC2FA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 64 kB flash microcontroller with 1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals |
| P89CV51RC2FA,512 | 功能描述:8位微控制器 -MCU 80C51 32K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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