參數資料
型號: P87LPC767HD
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: CONNECTOR ACCESSORY
中文描述: 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20
封裝: 7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20
文件頁數: 53/60頁
文件大小: 320K
代理商: P87LPC767HD
Philips Semiconductors
Product data
87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2001 Aug 07
50
COMPARATOR ELECTRICAL CHARACTERISTICS
V
DD
= 3.0 V to 6.0 V unless otherwise specified; T
amb
= 0
°
C to +70
°
C, –40
°
C to +85
°
C, or –40
°
C to +125
°
C, unless otherwise specified
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNIT
MIN
MAX
±
10
V
DD
–0.3
–50
V
IO
V
CR
CMRR
Offset voltage comparator inputs
1
mV
Common mode range comparator inputs
Common mode rejection ratio
1
0
V
dB
Response time
250
500
ns
μ
s
μ
A
Comparator enable to output valid
10
±
10
I
IL
Input leakage current, comparator
0 < V
IN
< V
DD
NOTE:
1. This parameter is guaranteed by characterization, but not tested in production.
A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
Vdd = 3.0 V to 6.0 V unless otherwise specified;
Tamb = 0 to +70
°
C for commercial, -40
°
C to +85
°
C for industrial, or –40
°
C to +125
°
C for extended industrial, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
MIN
MAX
V
DD
+ 0.2
tbd
15
±
1
±
1
±
1
±
1
±
1
±
1
-60
100
10
AV
IN
R
REF
C
IA
DL
e
IL
e
OS
e
G
e
A
e
M
CTC
C
t
-
-
Analog input voltage
Resistance between V
DD
and V
SS
Analog input capacitance
Differential non-linearity
1,2,3
Integral non-linearity
1,4
Offset error
1,5
Gain error
1,6
Absolute voltage error
1,7
Channel-to-channel matching
Crosstalk between inputs of port
8
Input slew rate
Input source impedance
V
SS
- 0.2
tbd
V
k
pF
LSB
LSB
LSB
%
LSB
LSB
dB
V/ms
k
A/D enabled
0 to 100 kHz
NOTES:
1. Conditions: V
SS
= 0 V; V
DD
= 5.12 V.
2. The A/D is monotonic, there are no missing codes
3. The differential non-linearity (DL
e
) is the difference between the actual step width and the ideal step width. See Figure 40.
4. The integral non-linearity (IL
e
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 40.
5. The offset error (OS
e
) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
the straight line which fits the ideal transfer curve. See Figure 40.
6. The gain error (G
e
) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 40.
7. The absolute voltage error (A
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
8. This should be considered when both analog and digital signals are input simultaneously to A/D pins.
9. Changing the input voltage faster than this may cause erroneous readings.
10.A source impedance higher than this driving an A/D input may result in loss of precision and erroneous readings.
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