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參數(shù)資料
| 型號： | P87LPC767HD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大小： | 320K |
| 代理商： | P87LPC767HD |
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Philips Semiconductors
Product data
87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2001 Aug 07
16
BIT
I2CON.7
“
I2CON.6
“
SYMBOL
RDAT
CXA
ATN
IDLE
FUNCTION
Read: the most recently received data bit.
Write: clears the transmit active flag.
Read: ATN = 1 if any of the flags DRDY, ARL, STP, or STP = 1.
Write: in the I
2
C slave mode, writing a 1 to this bit causes the I
2
C hardware to ignore the bus until it
is needed again.
Read: Data Ready flag, set when there is a rising edge on SCL.
Write: writing a 1 to this bit clears the DRDY flag.
Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode.
Write: writing a 1 to this bit clears the CARL flag.
Read: Start flag, set when a start condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STR flag.
Read: Stop flag, set when a stop condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STP flag.
Read: indicates whether this device is currently as bus master.
Write: writing a 1 to this bit causes a repeated start condition to be generated.
Read: undefined.
Write: writing a 1 to this bit causes a stop condition to be generated.
I2CON.5
“
I2CON.4
“
I2CON.3
“
I2CON.2
“
I2CON.1
“
I2CON.0
“
DRDY
CDR
ARL
CARL
STR
CSTR
STP
CSTP
MASTER
XSTR
—
XSTP
* Due to the manner in which bit addressing is implemented in the 80C51 family, the I2CON register should never be altered by
use of the SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to the fact that read and write functions of this register
are different. Testing of I2CON bits via the JB and JNB instructions is supported.
—
SU01155
MASTER
STP
STR
ARL
DRDY
ATN
RDAT
0
1
2
3
4
5
6
7
I2CON
Reset Value: 81h
Bit Addressable*
Address: D8h
XSTP
XSTR
CSTP
CSTR
CARL
CDR
IDLE
CXA
READ
WRITE
Figure 8. I
2
C Control Register (I2CON)
BIT
I2DAT.7
SYMBOL
RDAT
FUNCTION
Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading
I2DAT also clears DRDY and the Transmit Active state.
Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the
Transmit Active state.
Unused.
“
XDAT
I2DAT.6–0
–
—
SU01156
—
—
—
—
—
—
RDAT
0
1
2
3
4
5
6
7
I2DAT
Reset Value: xxh
Not Bit Addressable
Address: D9h
—
—
—
—
—
—
—
XDAT
READ
WRITE
Figure 9. I
2
C Data Register (
I
2DAT)
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