參數(shù)資料
型號(hào)： P87LPC767HD
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： CONNECTOR ACCESSORY
中文描述： 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20
封裝： 7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20
文件頁(yè)數(shù)： 33/60頁(yè)
文件大?。?/td> 320K
代理商： P87LPC767HD
Philips Semiconductors
Product data
87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2001 Aug 07
30
Low Voltage EPROM Operation
The EPROM array contains some analog circuits that are not
required when V
DD
is less than 4 V, but are required for a V
DD
greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
power down these analog circuits resulting in a reduced supply
current. LPEP is cleared only by power-on reset, so it may be set
ONLY for applications that always operate with V
DD
less than 4 V.
Reset
The 87LPC767 has an active low reset input when configured for an
external reset. A fully internal reset may also be configured which
provides a reset when power is initially applied to the device. The
watchdog timer can act as an oscillator fail detect because it uses
an independent, fully on-chip oscillator.
The external reset input is disabled, and fully internal reset
generation enabled, by programming the RPD bit in the EPROM
configuration register UCFG1 to 0. EPROM configuration is
described in the section EPROM Characteristics
SU01359
87LPC767
87LPC767
V
DD
8.2 k
10 F
RST
RST
2.2 F
Figure 22. Typical External Reset Circuits
SU01170
CHIP RESET
CPU
CLOCK
Q
RESET
TIMING
RPD (UCFG1.6)
WDT
MODULE
SOFTWARE RESET
SRST (AUXR1.3)
POWER MONITOR
RESET
RST/V
PP
PIN
WDTE (UCFG1.7)
S
R
Figure 23. Block Diagram Showing Reset Sources
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