參數(shù)資料
型號: P83C251TQ24
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 7/36頁
文件大?。?/td> 813K
代理商: P83C251TQ24
8xC251TB/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
9
PSEN#
O
Program Store Enable. Read signal output. This output is asserted for a
memory address range that depends on bits RD0 and RD1 in configu-
ration byte UCONFIG0 (see RD#).
RD#
O
Read or 17th Address Bit (A16). Read signal output to external data
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN#).
P3.7/A16
RST
I
Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port pins are
driven to their reset conditions when a voltage greater than VIH1 is
applied, whether or not the oscillator is running. This pin has an internal
pulldown resistor, which allows the device to be reset by connecting a
capacitor between this pin and VCC.
Asserting RST when the chip is in idle mode or powerdown mode returns
the chip to normal operation.
RXD
I/O
Receive Serial Data. RXD sends and receives data in serial I/O mode 0
and receives data in serial I/O modes 1, 2, and 3.
P3.0
RXD1
I/O
Receive Serial Data 1. RXD1 sends and receives data in serial I/O
mode 0 and receives data in serial I/O modes 1, 2, and 3 for the 2nd
serial port.
P1.2/ECI
T1:0
I
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter,
a falling edge on the T1:0 pin increments the count.
P3.5:4
T2
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is the
external clock input. For the clock-out mode, it is the timer 2 clock output.
P1.0
T2EX
I
Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a
capture of the timer 2 registers. In auto-reload mode, a falling edge
causes the timer 2 registers to be reloaded. In the up-down counter
mode, this signal determines the count direction: 1 = up, 0 = down.
P1.1
TXD
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0
and transmits serial data in serial I/O modes 1, 2, and 3.
P3.1
TXD1
O
Transmit Serial Data 1. TXD1 outputs the shift clock in serial I/O mode 0
and transmits serial data in serial I/O modes 1, 2, and 3 for the 2nd serial
port.
P1.3/CEX0
VCC
PWR
Supply Voltage. Connect this pin to the +5V supply voltage.
VCC2
PWR
Secondary Supply Voltage 2. This supply voltage connection is
provided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB as
a pin-for-pin replacement for the 8XC51FX, V
SS
2 can be unconnected
without loss of compatibility. (Not available on DIP)
VSS
GND
Circuit Ground. Connect this pin to ground.
VSS1
GND
Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground is
recommended. However, when using the 8xC251TB/TQ as a pin-for-pin
replacement for the 8XC51BH, VSS1 can be unconnected without loss of
compatibility. (Not available on DIP)
Table 6. Signal Descriptions (Sheet 2 of 3)
Signal
Name
Type
Description
Alternate
Function
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