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參數(shù)資料
| 型號： | P83C251TQ24 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 813K |
| 代理商： | P83C251TQ24 |
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8xC251TB/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
17
TAVWL1
Address (mux’d) Valid to
WR# Low
@ 16MHz
@ 24MHz
85
43.4
(1+M)
2TOSC-40
ns (3,4)
TAVWL1A
Address (mux’d) Valid to
WR# Low
@ 16MHz
@ 24MHz
72.5
51.7
(0.5+M)
2TOSC+10
ns (3,5)
TAVWL2
Address (demux’d) Valid to
WR# Low
@ 16MHz
@ 24MHz
108
66.4
(1+M)
2TOSC-17
ns (3,4)
TAVWL2A
Address (demux’d) Valid to
WR# Low
@ 16MHz
@ 24MHz
135
93.4
(1+M)
2TOSC+10
ns (3,5)
TWHQX
Data Hold after WR# High
@ 16MHz
@ 24MHz
49.5
28.7
TOSC-13
ns
TQVWH
Data Valid to WR# High
@ 16MHz
@ 24MHz
110
68.4
(1+N)
2TOSC-15
ns (3)
TWHAX
WR# High to Address Hold
@ 16MHz
@ 24MHz
112
70.4
2TOSC-13
ns
NOTES:
1. 24 MHz XTAL Frequency.
2. Specifications for PSEN# are identical to those for RD#.
3. In the formula, M = number of wait states (0 or 1) for ALE and N = Number of wait states (0,1,2 or 3) for
RD#/PSEN#/WR#.
4. Device configured with the default data float timing for fast memory interface (EDF# = 1).
5. Device configured with extended data float timing for slow memory interface (EDF# = 0).
Table 11. AC Characteristics (Sheet 4 of 4)
Symbol
Parameter
@ Max FOSC (1)
FOSC Variable
Units
Min
Max
Min
Max
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