- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄367700 > P610ARM-FPNR (Zarlink Semiconductor Inc.) General purpose 32-bit microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | P610ARM-FPNR |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 97/173頁(yè) |
| 文件大小： | 897K |
| 代理商： | P610ARM-FPNR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)當(dāng)前第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)
Instruction and Data Cache (IDC)
ARM610 Data Sheet
6-3
6.4.2 Uncacheable reads
C = 0
The cache is not searched for the relevant data; instead an external memory access
is initiated. No linefetch operation is performed, and the cache is not updated.
6.4.3 Updateable writes
U = 1
An external memory access is initiated, and the cache is searched; if the cache holds
a copy of the data from the address being written to, then the cache data is
simultaneously updated.
6.4.4 Non-updateable writes
U = 0
An external memory access is initiated, but the cache is not searched and the contents
of the cache are not affected.
6.5
IDC Validity
The IDC operates with virtual addresses, so care must be taken to ensure that its
contents remain consistent with the virtual to physical mappings performed by the
Memory Management Unit. If the Memory Mappings are changed, the IDC validity
must be ensured.
6.5.1 Software IDC flush
The entire IDC may be marked as invalid by writing to the ARM610 IDC Flush Register
(Register 7). The cache will be flushed immediately the register is written, but note that
the following two instruction fetches may come from the cache before the register is
written.
6.5.2 Doubly mapped space
Since the cache works with virtual addresses, it is assumed that every virtual address
maps to a different physical address. If the same physical location is accessed by more
than one virtual address, the cache cannot maintain consistency, since each virtual
address will have a separate entry in the cache, and only one entry will be updated on
a processor write operation. To avoid any cache inconsistencies, both doubly-mapped
virtual addresses should be marked as uncacheable.
6.6
Read-Lock-Write
The IDC treats the Read-Locked-Write instruction as a special case. The read phase
always forces a read of external memory, regardless of whether the data is contained
in the cache. The write phase is treated as a normal write operation (and if marked as
updateable, and the data is already in the cache, the cache will be updated). Externally
the two phases are flagged as indivisible by asserting the
LOCK
signal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P610ARM-B | General purpose 32-bit microprocessor |
| P610ARM-KG | General purpose 32-bit microprocessor |
| P610ARM-KW | General purpose 32-bit microprocessor |
| P6121-AU120 | Incremental Encoders |
| P6111-AP120 | Incremental Encoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P610ARM-KG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KW | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P6-10R | 制造商:Panduit Corp 功能描述:PANDUIT |
| P6-10R-E | 功能描述:端子 NON-INSL.RING #6 #10 RoHS:否 制造商:AVX 產(chǎn)品:Junction Box - Wire to Wire 系列:9826 線規(guī):26-18 接線柱/接頭大小: 絕緣: 顏色:Red 型式:Female 觸點(diǎn)電鍍:Tin over Nickel 觸點(diǎn)材料:Beryllium Copper, Phosphor Bronze 端接類型:Crimp |
| P610R-E | 制造商:Panduit Corp 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。