參數(shù)資料
型號: P610ARM-FPNR
廠商: Zarlink Semiconductor Inc.
英文描述: General purpose 32-bit microprocessor
中文描述: 通用32位微處理器
文件頁數(shù): 69/173頁
文件大?。?/td> 897K
代理商: P610ARM-FPNR
Instruction Set - LDM, STM
ARM610 Data Sheet
4-41
O
4.9.8 Assembler syntax
<LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^}
where:
{cond}
two character condition mnemonic. See
·
Table 4-2: Condition code
summaryon page 4-6.
Rn
is an expression evaluating to a valid register number
<Rlist>
is a list of registers and register ranges enclosed in {} (e.g. {R0,R2-
R7,R10}).
{!}
if present requests write-back (W=1), otherwise W=0
{^}
if present set S bit to load the CPSR along with the PC, or force
transfer of user bank when in privileged mode
Addressing mode names
There are different assembler mnemonics for each of the addressing modes,
depending on whether the instruction is being used to support stacks or for other
purposes. The equivalence between the names and the values of the bits in the
instruction are shown in the following table:
FD, ED, FA, EA define pre/post indexing and the up/down bit by reference to the form
of stack required. The F and E refer to a “full” or “empty” stack, i.e. whether a pre-index
has to be done (full) before storing to the stack. The A and D refer to whether the stack
is ascending or descending. If ascending, a STM will go up and LDM down, if
descending, vice-versa.
IA, IB, DA, DB allow control when LDM/STM are not being used for stacks and simply
mean Increment After, Increment Before, Decrement After, Decrement Before.
Name
Stack
Other
L bit
P bit
U bit
pre-increment load
LDMED
LDMIB
1
1
1
post-increment load
LDMFD
LDMIA
1
0
1
pre-decrement load
LDMEA
LDMDB
1
1
0
post-decrement load
LDMFA
LDMDA
1
0
0
pre-increment store
STMFA
STMIB
0
1
1
post-increment store
STMEA
STMIA
0
0
1
pre-decrement store
STMFD
STMDB
0
1
0
post-decrement store
STMED
STMDA
0
0
0
Table 4-4: Addressing mode names
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