參數(shù)資料
型號： P610ARM-FPNR
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 14/173頁
文件大小： 897K
代理商： P610ARM-FPNR
Signal Description
ARM610 Data Sheet
2-2
2.1
Signal Description
Key to Signal Types
IT
Input, TTL threshold
OCZ
Output, CMOS levels, tristateable
ITOTZ
Input/output tristateable, TTL thresholds
ICK
Input, clock levels
Name
Type
Description
A[31:0]
OCZ
Address Bus. This bus signals the address requested for memory
accesses. Normally it changes during
MCLK
HIGH.
ABE
IT
Address bus enable. When this input is LOW, the address bus
nRW
,
nBW
and
LOCK
are put into a high impedance state (Note 1).
A[31:0]
,
ABORT
IT
External abort. Allows the memory system to tell the processor that a
requested access has failed. Only monitored when
external memory.
ARM610
is accessing
ALE
IT
Address latch enable. This input is used to control transparent latches on
the address bus
A[31:0]
,
nBWTT
,
nRW
change during
MCLK
HIGH, but they may be held by driving
See
·
13.2.2 Tald measurement on page 13-3
and
LOCK
. Normally these signals
ALE
LOW.
.
D[31:0]
ITOTZ
Data bus. These are bidirectional signal paths used for data transfers
between the processor and external memory. For read operations (when
nRW
is LOW), the input data must be valid before the falling edge of
MCLK
. For write operations (when
nRW
become valid while
MCLK
is LOW. At high clock frequencies the data may
not become valid until just after the
MCLK
Signals on page 13-3
).
is HIGH), the output data will
rising edge (see
·
13.3 Main Bus
DBE
IT
Data bus enable. When this input is LOW, the data bus,
a high impedance state (Note 1). The drivers will always be high
impedance except during write operations, and
in systems which do not require the data bus for DMA or similar activities.
D[31:0]
is put into
DBE
must be driven HIGH
FCLK
ICK
Fast clock input. When the
performing an internal cycle, it is clocked with the Fast Clock,
ARM610
CPU is accessing the cache or
FCLK
.
LOCK
OCZ
Locked operation.
access sequence, and the memory manager should wait until
LOW before allowing another device to access the memory.
changes while
MCLK
is HIGH and remains HIGH during the locked
memory sequence.
LOCK
is latched by
LOCK
is driven HIGH, to signal a
locked
memory
LOCK
LOCK
goes
ALE
.
MCLK
ICK
Memory clock input. This clock times all
LOW or HIGH period of
alternatively, the
nWAIT
achieve similar effects.
ARM610
memory accesses. The
MCLK
input may be used with a free-running
may be stretched for slow peripherals;
MCLK
to
Table 2-1: Signal descriptions
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