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| 型號(hào)： | P60ARM-IG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁(yè)數(shù)： | 54/120頁(yè) |
| 文件大?。?/td> | 1275K |
| 代理商： | P60ARM-IG |
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P60ARM-B
50
4.10 Software interrupt (SWI)
The instruction is only executed if the condition is true. The various conditions are defined at the beginning
of this chapter. The instruction encoding is shown in
Figure 24: Software Interrupt Instruction
.
The software interrupt instruction is used to enter Supervisor mode in a controlled manner. The instruction
causes the software interrupt trap to be taken, which effects the mode change. The PC is then forced to a
fixed value (0x08) and the CPSR is saved in SPSR_svc. If the SWI vector address is suitably protected (by
external memory management hardware) from modification by the user, a fully protected operating system
may be constructed.
Figure 24: Software Interrupt Instruction
4.10.1 Return from the supervisor
The PC is saved in R14_svc upon entering the software interrupt trap, with the PC adjusted to point to the
word after the SWI instruction. MOVS PC,R14_svc will return to the calling program and restore the CPSR.
Note that the link mechanism is not re-entrant, so if the supervisor code wishes to use software interrupts
within itself it must first save a copy of the return address and SPSR.
4.10.2 Comment Teld
The bottom 24 bits of the instruction are ignored by the processor, and may be used to communicate
information to the supervisor code. For instance, the supervisor may look at this field and use it to index
into an array of entry points for routines which perform the various supervisor functions.
4.10.3 Instruction Cycle Times
Software interrupt instructions take 2S + 1N incremental cycles to execute, where S and N are as defined
in section 5.1 Cycle types on page 65.
4.10.4 Assembler syntax
SWI{cond} <expression>
{cond} - two character condition mnemonic, see
Figure 6: Condition Codes
<expression> is evaluated and placed in the comment field (which is ignored by ARM60).
31
28 27
24 23
0
Condition field
1111
Cond
Comment field (ignored by Processor)
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