參數(shù)資料
型號(hào)： P60ARM-IG
廠商： Zarlink Semiconductor Inc.
英文描述： Low power, general purpose 32-bit RISC microprocessor
中文描述： 低功耗，通用32位RISC微處理器
文件頁數(shù)： 15/120頁
文件大?。?/td> 1275K
代理商： P60ARM-IG
Programmer's Model
11
Figure 3: Register Organisation
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). Many FIQ programs will not need
to save any registers. User mode, IRQ mode, Supervisor mode,
two banked registers mapped to R13 and R14. The two banked registers allow these modes to each have a
private stack pointer and link register. Supervisor, IRQ,
require more than these two banked registers are expected to save some or all of the caller's registers (R0 to
R12) on their respective stacks. They are then free to use these registers which they will restore before
returning to the caller. In addition there are also five SPSRs (Saved Program Status Registers) which are
loaded with the CPSR when an exception occurs. There is one SPSR for each privileged mode. Thus the
CPSR of the calling mode can be easily restored when the current (privileged) mode is exited.
Abort mode and Undefined mode each have
Abort and Undefined mode programs which
General Registers and Program Counter
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_svc
R14_svc
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_abt
R14_abt
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_irq
R14_irq
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_und
R14_und
R15 (PC)
User32
FIQ32
Supervisor32
Abort32
IRQ32
Undefined32
CPSR
CPSR
SPSR_fiq
CPSR
SPSR_svc
CPSR
SPSR_abt
CPSR
SPSR_irq
CPSR
SPSR_und
Program Status Registers
相關(guān)PDF資料
PDF描述
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