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參數(shù)資料
| 型號(hào)： | P4C1024-35C6M |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 35 ns, CDIP32 |
| 封裝： | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 152K |
| 代理商： | P4C1024-35C6M |
P4C1024
Page 7 of 14
Document # SRAM124 REV A
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CE CONTROLLED)(11)
1.5V
Write
Active
Read
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1024, care must be
taken when testing this device; an inadequate setup can cause a
normal functioning part to be rejected as faulty.
Long high-
inductance leads that cause supply bounce must be avoided by
bringing the V
CC and ground planes directly up to the contactor
fingers.
A 0.01 F high frequency capacitor is also required
between V
CC and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50
test environment should be terminated into a 50 load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116
resistor must be used in series with D
OUT to match 166 (Thevenin
Resistance).
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
See Fig. 1 and 2
Mode
Standby
D
OUT Disabled
Standby
Power
I/O
WE
OE
CE
2
CE
1
High Z
D
OUT
High Z
X
H
L
X
H
L
X
L
H
X
L
Standby
Active
High Z
Figure 1. Output Load
Figure 2. Thevenin Equivalent
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