參數(shù)資料
型號(hào)： P13683EJ2V0AN00
英文描述： uPC8106. uPC8109 and uPC8163 2.0GHz Silicon Frequency Up-converter ICs for Mobile Communications
中文描述： uPC8106。 uPC8109硅和uPC8163 2.0GHz的頻率上移動(dòng)通信轉(zhuǎn)換器IC
文件頁(yè)數(shù)： 10/59頁(yè)
文件大?。?/td> 447K
代理商： P13683EJ2V0AN00
Application Note P13683EJ2V0AN00
10
4.
EXTERNAL CIRCUIT CONFIGURATION
4.1 Impedance Matching at RF Output
Since this IC has an open-collector output, an external LC matching circuit for RF should be included in the circuit
configuration. The matching circuit should include a parallel inductor to the V
CC
side and a series capacitor to the
next stage. As mentioned earlier, the bias of the output pin’s collector is applied via the inductor used for RF
matching of the V
CC
pin’s voltage. In other words, the inductor that is connected to the output pin has two effects: its
RF effect (frequency matching) and its DC effect (application of bias). For this reason, the external inductor should
be a small DC-resistance and high frequency use type.
The LC matching circuit constants used in the test circuits shown in the data sheet are for the evaluation board
described in the data sheet. This evaluation board is used only for simple evaluations; devices evaluated using this
board are not immediately suitable for application in systems. The patterns used for evaluation do not allow parts to
be mounted near the IC, so the pattern size is larger. Accordingly, these are not the recommended patterns or the
recommended circuit constants.
The matching LC value is determined so as to produce a narrow-band power gain that suits the frequency
bandwidth used, based on the IC’s own S parameters. Select a value that reduces the S
22
value to about –20 dBm
when the gain within the frequency bandwidth used is at the maximum. A 900 MHz high pass type and a 1.5 GHz
and 1.9 GHz low pass type are shown as example of an RF matching circuit configuration.
4.2 Input Impedance Matching
The IF and LO inputs in this IC are base inputs with parallel connections to bias resistors. Although their
characteristic impedance is not 50
, the test circuits in the data sheet show a signal generator with a 50
signal
source impedance. Accordingly, the data sheet’s electrical characteristics include loss due to this mismatched
impedance. If impedance matching is implemented in the actual circuit, the elimination of this loss raises the IC’s
input level, which lowers the required input level (by about 3 to 5 dB). When configuring an IF matching circuit, such
as is shown in Figure 4-1, the response time varies according to the IF matching circuit’s DC cut series capacitance
value (see
5.1 Operating Rise/Fall Times
).
Figure 4-3 shows S parameter values for RF, IF, and LO ports when matching is not implemented. Although the
internal components are the same in the T and TB products, the packages, leads, and chip sizes are different, which
means that the S parameters are slightly different, so some optimization is needed (concerning peripheral circuit
constants, mounting pads, etc.) when replacing one package with the other.
4.3 Bypass Capacitor
As in other ICs, in this IC the V
CC
pin must be GND in RF, so externally attach a bypass capacitor with a large
value such as 1 000 pF. In the
μ
PC8106 and
μ
PC8109, the conversion value is higher or lower depending on the
board. This difference is based on the relationship between the IC’s internal elements and board, and the pattern
length. If the conversion gain on the board of the actual set is low, it can be improved by inserting an external chip
capacitor of about 100 pF between the V
CC
and PS pins to readjust the matching.
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