參數(shù)資料
      型號: ORT82G5-3F680C
      廠商: Lattice Semiconductor Corporation
      文件頁數(shù): 38/119頁
      文件大?。?/td> 0K
      描述: IC FPSC TRANSCEIVER 8CH 680-BGA
      產(chǎn)品變化通告: Product Discontinuation 01/Aug/2011
      標(biāo)準(zhǔn)包裝: 24
      系列: *
      Lattice Semiconductor
      ORCA ORT42G5 and ORT82G5 Data Sheet
      25
      Figure 9. Fibre Channel Link State Machine State Diagram
      XAUI Link Synchronization Function
      For each lane, the receive section of the XAUI link state machine incorporates a synchronization state machine that
      monitors the status of the 10-bit alignment. A 10-bit alignment is done in the SERDES based on a comma charac-
      ter such as K28.5. A comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that can-
      not appear across the boundary between any two valid 10-bit code-groups. This property makes the comma useful
      for delimiting code-groups in a serial stream.This mechanism incorporates a hysteresis to prevent false synchroni-
      zation and loss of synchronization due to infrequent bit errors. For each lane, the sync_complete signal is disabled
      until the lane achieves synchronization. The synchronization state diagram is shown in Figure 10. This state
      machine is modeled after draft IEEE 802.3ae, version 2.1 but will also operate with version 4.1 implementations.
      Table 4 and Table 5 describe the state variables used in Figure 10. The XAUI state machine does not have any
      control over the SERDES byte aligner. It is the user’s responsibility to control the byte aligner through software
      access of register map addresses 30800 and 30900.
      Note that it takes four idle ordered sets (e.g. K28.5, Dxx.y, Dxx.y, Dxx.y) to bring the state machine from a
      loss_of_sync to a synch_acq’d_1 state. When back-to-back commas are used instead, it takes a total of ve com-
      mas to achieve the same result as with idle ordered sets.
      Table 4. XAUI Link Synchronization State Diagram – Functions
      Function
      Description
      sync_complete
      Indication that alignment code-group alignment has been established at the boundary indicated by the
      most recently received comma.
      cg_comma
      Indication that a valid code-group, with correct running disparity, containing a comma has been received.
      cg_good
      Indication that a valid code-group with the correct running disparity has been received.
      cg_bad
      Indication that an invalid code-group has been received.
      no_comma
      Indication that comma timer has expired. The timer is initialized upon receipt of a comma.
      LOS = 1
      LAST ORDERED SET RECEIVED:
      VW
      RST
      LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1)
      OS
      CV
      OS
      CV
      1VW
      2 VW
      a
      b
      c
      d
      e
      h
      g
      f
      LOSS OF SYNCHRONIZATION (WDSYNC_XX = 0)
      LSM_ENABLE
      +
      POWERUP_RESET
      VW: VALID WORD (A 4 CHARACTER BASED WORD HAVING NO CODE VIOLATION) WITH AT LEAST
      CV: CODE VIOLATION (RUNNING DISPARITY BASED ON ILLEGAL COMMA POSITION)
      OS: IDLE ORDERED SET (A 4 CHARACTER BASED WORD HAVING COMMA AS THE 1ST CHARACTER)
      1VW: FIRST VALID WORD AFTER A CODE VIOLATION
      TWO PRECEEDING VALID WORDS
      2VW: SECOND VALID WORD AFTER A CODE VIOLATION
      相關(guān)PDF資料
      PDF描述
      ORT8850L-1BMN680I IC TRANCEIVERS FPSC 680FPGAM
      ORT8850L-3BM680C IC FPSC TRANSCEIVER 8CH 680-BGA
      P1010PSE5HFA MPU PROTO 800/667 425-TEPBGA1
      P1013NXN2LFB IC MPU 1067MHZ 689TEPBGA
      P1013PSE2EFA IC MPU PROTO 600MHZ 689-TEPBGA
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      ORT82G5-3FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
      ORT82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
      ORT82G5-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
      ORT82G5-G2-PAC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORT82G5 ispGDX256 is pPAC PwrMgr 1208 BC RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
      ORT8850 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver