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| 型號(hào)： | ORT82G5-3F680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 37/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
24
Figure 8. Receive DEMUX Block for a Single SERDES Channel
One clock per block of two or four channels, called RCK78[A,B], is sent to the FPGA. The control bits RCKSEL[A,B]
are used to select the channel that is the source for these clocks.
Link State Machines
Two link state machines are included in the device, one for XAUI applications and a second for Fibre Channel appli-
cations.
The Fibre Channel link state machine is responsible for establishing a valid link between the transmitter and the
receiver and for maintaining link synchronization. The machine is initially in the Loss Of Synchronization (LOS)
state upon power-on reset. This is indicated by WDSYNC_xx = 0. While in this state, the machine looks for a partic-
ular number of consecutive idle ordered sets without any invalid data transmission in between before declaring syn-
chronization achieved. Achievement of synchronization is indicated by asserting WDSYNC_xx = 1. Specically, the
machine looks for three continuous idle ordered sets without any misaligned comma character or any running dis-
parity based code violation in between. In the event of any such code violation, the machine would reset itself to the
ground state and start its search for the idle ordered sets again. A typical valid sequence for achieving link synchro-
nization would be K28.5 D21.4 D21.5 D21.5 repeated three times.
In the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of
code violation that might result due to running disparity errors. If it were to receive four such consecutive invalid
words, the link machine loses its synchronization and once again enters the loss of synchronization state (LOS). A
pair of valid words received by the machine overcomes the effect of a previously encountered code violation. LOS
is indicated by the status of WDSYNC_xx output which now transitions from 1 to 0. At this point the machine
attempts to establish the link yet again. Figure 9 shows the state diagram for the Fibre Channel link state machine.
LOS is also indicated by DEMUXWAS_xx status register bit. This bit is set to 0 during loss of synchronization.
pq
r
s
t
x
y
z
SRBDxx[9:0]
10-bit
p
7-0
40-bit
RWD_xx[31:24]
RWD_xx[23:16]
RWD_xx[15:8]
RWD_xx[7:0]
LATENCY = 4 RSYS_CLK [A1,...,B2] CLOCKS
p
8
p
9
t
7-0
t
8
t
9
q
7-0
q
8
q
9
x
7-0
x
8
x
9
r
7-0
r
8
r
9
y
7-0
y
8
y
9
s
7-0
s
8
s
9
z
7-0
z
8
z
9
RWBIT8_xx[3]
RWBIT9_xx[3]
RWBIT8_xx[2]
RWBIT8_xx[1]
RWBIT8_xx[0]
RWBIT9_xx[2]
RWBIT9_xx[1]
RWBIT9_xx[0]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORT82G5 ispGDX256 is pPAC PwrMgr 1208 BC RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
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