- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1958 > ORT82G5-3F680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ORT82G5-3F680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 34/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)當(dāng)前第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
21
Bit alignment times fall into two categories: realignment when the input serial data stream experiences an abrupt
phase change (as may occur when protection switching is performed between two paths having different delays),
and alignment from a no-signal condition. Realignment is very quick, since the PLL’s VCO is already locked on fre-
quency and only needs to adapt to the new phase. This re-alignment has been observed to require no more than
one microsecond when REFCLK[A:B] = 156.25 MHz.
Alignment from a no-signal condition has two components. First, there is the re-acquisition to the data’s frequency
and phase. The time required for re-acquisition to the data’s frequency is minimized by logic that periodically
switches the PLL to lock to the REFCLK[A:B] when it fails to lock on the serial data stream, thus limiting the VCO’s
frequency wander. Second, there is the time spent while the PLL is locking to REFCLK[A:B], which can be from
zero to a maximum value, depending on when the serial data stream becomes valid in relation to the PLL’s switch-
ing to/from REFCLK[A:B]. This alignment has been observed to require no more than 4 microseconds when REF-
CLK = 156.25 MHz.
Byte alignment occurs once valid bit alignment is achieved. The byte aligner looks for a particular 7-bit sequence
(either 0011111 or its complement, 1100000) that, in data that has been 8b/10b encoded per Fibre Channel or
IEEE 802.3ae specications, only occurs in the comma (/K/) characters K28.1, K28.5 and K28.7. Byte alignment
only occurs when the ENBYSYNC_xx signal for that channel is active high, and re-alignment occurs on each 7-bit
sequence encountered. However, if ENBYSYNC_xx is asserted active high and no comma character is encoun-
tered, and then is brought inactive low, the channel will still perform one byte alignment operation on the next
comma character. Byte alignment occurs immediately when an alignment sequence is detected, so the lock time is
only one clock period.
Note: Each time the byte aligner performs an alignment, it also corrects the phase of the internal RBC_xx clock.
This can result in the “stretching” of the clock by a half-phase in order to cause the output data to align with the ris-
ing edge of RBC_xx.
Word (32-bit) alignment can occur after the Fibre Channel (XAUI_MODE_xx = 0) or XAUI (XAUI_MODE_xx = 1)
state machine has reached the in-synchronization state. In Fibre Channel mode, synchronization (WDSYNC_xx =
1) will occur after three ordered sets of data have been received in the absence of any code violations. After this,
the next ordered set will cause the output data to be aligned such that the comma character is in the most signi-
cant byte. Thus, 32-bit word alignment has been achieved when four ordered sets have been detected. The time
required is directly dependent on comma-character density.
Note: once word alignment is accomplished, no further alignment occurs unless and until WDSYNC_xx goes to
zero and back to one again. Comma characters that are not located in the most signicant byte position will not
trigger further re-alignment while WDSYNC_xx is active. This behavior is as dened by the Fibre Channel speci-
cation. However, it means that, if the channel experiences an abrupt delay change (as could occur if an external
MUX performs a protection switch between two links) and if the delay change is close enough to a full character or
characters that not enough code violations are generated to cause loss of WDSYNC_xx, the channel could
become misaligned and remain that way indenitely. As mentioned above, this behavior is that dened by the Fibre
Channel specication.
In XAUI mode, as the state diagram later in this data sheet indicates, three error-free code-groups containing com-
mas must be detected before synchronization is declared.
Multi 2, 4 or 8 (ORT82G5 only) channel alignment (Lane alignment in XAUI mode) can be performed after 32-
bit word alignment is complete. Multi-channel alignment is described in later sections of this data sheet.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT8850L-1BMN680I | IC TRANCEIVERS FPSC 680FPGAM |
| ORT8850L-3BM680C | IC FPSC TRANSCEIVER 8CH 680-BGA |
| P1010PSE5HFA | MPU PROTO 800/667 425-TEPBGA1 |
| P1013NXN2LFB | IC MPU 1067MHZ 689TEPBGA |
| P1013PSE2EFA | IC MPU PROTO 600MHZ 689-TEPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-3FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORT82G5 ispGDX256 is pPAC PwrMgr 1208 BC RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。