參數資料
型號： ORLI10G2BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數： 29/78頁
文件大?。?/td> 1689K
代理商： ORLI10G2BM680-DB
Lattice Semiconductor
ORCA ORLI10G Data Sheet
35
LVDS Receiver Buffer Requirements
Table 9. Receiver ac Data*
* Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 C - 125 C.
Table 10. Receiver Power Consumption*
* Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 C - 125 C.
Table 11. Receiver dc Data*
* Characterized at VDD33 = 3.1 V—3.5 V, VDD15 = 1.425 V—1.575 V, TJ = –40 C - 125 C.
External reference, REF10 = 1.0 V ± 3%, REF14 = 1.4 V ± 3%.
Table 12. LVDS Operating Parameters
Note: Under worst-case operating condition, the LVDS driver will withstand a disabled or unpowered receiver for an unlimited period of time
without being damaged. Similarly, when outputs are short-circuited to each other or to ground, the LVDS will not suffer permanent dam-
age. The LVDS driver supports hot insertion. Under a well-controlled environment, the LVDS I/O can drive backplane as well as cable.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Pulse-width Distortion
tPWD
VIDTH = 100 mV, 311 MHz
—
160
ps
Propagation Delay Time
tPLH
tPHL
CL = 0.5 pF
0.60
1.42
1.47
ns
With Common-mode Variation (0 V to 2.4 V)
tPD
CL = 0.5 pF
—
50
ps
Output Rise Time, 20% to 80%
tR
CL = 0.5 pF
150
350
ps
Output Fall Time, 80% to 20%
tF
CL = 0.5 pF
150
350
ps
Parameter
Symbol
Test Conditions
Min
Max
Unit
Receiver dc Power
PRdc
dc
—
20.4
mW
Receiver ac Power
PRac
ac
CL = 1.5 pF
—
4.5
W/MHz
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Voltage Range, VIA or VIA
VI
| VGPD| < 925 mV
dc – 1 MHz
0.0
1.2
2.4
V
Input Differential Threshold
VIDTH
| VGPD| < 925 mV
400 MHz
–100
—
100
mV
Input Differential Hysteresis
VHYST
(+VIDTHH) – (–VIDTHL)
25
—
mV
Receiver Differential Input Impedance
RIN
With build-in termination, center-
tapped
80
100
120
W
Parameter
Test Conditions
Min
Normal
Max
Unit
Transmit Termination Resistor
—
80
100
120
W
Receiver Termination Resistor
—
80
100
120
W
Temperature Range (TJ)
—
– 40
—
125
°C
Power Supply VDD33
—
3.1
—
3.5
V
Power Supply VDD15
—
1.4
—
1.6
V
Power Supply VSS
—
0
—
V
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相關代理商/技術參數
參數描述
ORLI10G-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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