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Table of Contents
Contents
Page
Contents
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2
Lattice Semiconductor
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
Introduction..................................................................1
Embedded Function Features .....................................4
Intellectual Property Features......................................4
Programmable Features..............................................4
Programmable Logic System Features .......................6
Description...................................................................7
FPSC Definition .........................................................7
FPSC Overview .........................................................7
FPSC Gate Counting ................................................7
FPGA/Embedded Core Interface ..............................7
ORCA Foundry Development System ......................7
FPSC Design Kit .......................................................8
FPGA Logic Overview ...............................................8
PLC Logic ..................................................................8
Programmable I/O .....................................................9
Routing ......................................................................9
System-Level Features..............................................10
Microprocessor Interface ...........................................10
System Bus .............................................................10
Phase-Locked Loops ..............................................10
Embedded Block RAM ............................................10
Configuration ...........................................................11
Additional Information .............................................11
ORLI10G Overview ...................................................11
Device Layout .........................................................11
10G Mode ...............................................................11
2.5G Mode ..............................................................12
Receive Path Details .................................................15
Line Interface ..........................................................15
DeMUX ....................................................................15
Onboard Receive PLLs ...........................................15
Transmit Path Details ................................................17
MUX ........................................................................17
Onboard Transmit PLLs ..........................................17
Line Interface ..........................................................17
ORLI10G Demultiplexer (Rx) Detail ..........................19
ORLI10G Multiplexer (Tx) Detail ...............................25
ORLI10G Embedded PLLs........................................31
ORLI10G Embedded Programmable PLLs
Specifications............................................................32
ORLI10G Reset Requirements..................................32
Line Interface Circuit Specifications ..........................33
Power Supply Decoupling LC Circuit ......................33
XGMII ORCA 4E Receive Analysis ...........................34
XGMII Considerations .............................................34
Absolute Maximum Ratings.......................................35
Recommended Operating Conditions .......................35
Embedded Core LVDS I/O ....................................... 36
LVDS Receiver Buffer Requirements ..................... 37
Timing Characteristics .............................................. 38
Receive Input Data Interface .................................. 38
Transmit STS-48/STS-192 (2.5G/10G) Data
Outputs ................................................................. 39
Input/Output Buffer Measurement Conditions
(Non-LVDS Buffer)................................................... 40
LVDS Buffer Characteristics..................................... 41
Termination Resistor .............................................. 41
LVDS Driver Buffer Capabilities ............................. 41
Pin Information ......................................................... 42
Pin Descriptions ..................................................... 42
Package Pinouts .................................................... 48
Package Thermal Characteristics Summary ............ 68
ΘJA ........................................................................ 68
ψJC ........................................................................ 68
ΘJC ........................................................................ 68
ΘJB ........................................................................ 68
FPSC Maximum Junction Temperature ................. 68
Package Thermal Characteristics............................. 69
Heat Sink Vendors for BGA Packages ..................... 69
Package Coplanarity ................................................ 69
Package Parasitics ................................................... 70
Package Outline Diagrams....................................... 71
Terms and Definitions ............................................ 71
416-Pin PBGAM ..................................................... 72
680-Pin PBGAM ..................................................... 73
Hardware Ordering Information ................................ 74
Software Ordering Information ................................. 74