參數(shù)資料
型號(hào)： ORLI10G-1BM680I
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, MULTILAYER, BGA-680
文件頁(yè)數(shù)： 42/74頁(yè)
文件大?。?/td> 1411K
代理商： ORLI10G-1BM680I
Agere Systems Inc.
47
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
Pin Information (continued)
Package Pinouts
Table 15 provides the number of user programmable I/Os available for each available package.
Table 19 provides the package pin and pin function for the ORLI10G FPSC and packages. The bond pad name is
identified in the PIO nomeclature used in the ORCA Foundry design editor. The bank column provides information
as to which output voltage level bank the given pin is in. The group column provides information as to the group of
pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-
ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then
the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
Table 18. ORCA Programmable I/Os Summary
It is very important to note the pinout limitations for 10 Gbits/s Ethernet applications. Specifically, the very stringent
timing requirements of the XGMII specification coupled with the I/O availability and locations in the 416-pin PBGA
requires that the XGMII output pins be located on three sides of the device. This may cause issues with routing the
XGMII bus at a board level as the XGMII specification for routing this bus on a board is only 2 in.
In addition, the built-in microprocessor interface (MPI) cannot be fully utilized in the 416-pin PBGA and the 680-pin
PBGA packages because the implementation of the XGMII interface limits the number of available address and
data pins.
As shown in the Pair columns in Table 19, differential pairs and physical locations are numbered within each bank
(e.g., L19C_A0 is the nineteenth pair in an associated bank). A C indicates complementary differential whereas a
T indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or verti-
cal direction. Other physical indicators are as follows:
s
_A1 indicates one ball between pairs.
s
_A2 indicates two balls between pairs.
s
_D0 indicates balls are diagonally adjacent.
s
_D1 indicates balls are diagonally adjacent separated by one physical ball.
VREF pins, shown in the Pin Description column in Table 19, are associated to the bank and group
(e.g., VREF_TL_01 is the VREF for group one of the top left (TL) bank).
Device
416 PBGAM1
680 PBGAM1
user programmable I/O
192
316
Available programmable differential pairs
184
272
FPGA configuration pins
7
FPGA dedicated function pins
2
Core function pins
86
VDD15
28
84
VDD33_A
4
VDDIO
21
44
VSS
48
95
VSS_A
4
LVCTAP For dedicated differential channels
6
Core LV_REF pins
4
Total Package pins
416
680
相關(guān)PDF資料
PDF描述
ORLI10G-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-1BM416I FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BMN416I FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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