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參數(shù)資料
| 型號(hào)： | ORLI10G-1BM680I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封裝： | PLASTIC, MULTILAYER, BGA-680 |
| 文件頁數(shù)： | 4/74頁 |
| 文件大?。?/td> | 1411K |
| 代理商： | ORLI10G-1BM680I |
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12
Agere Systems Inc.
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
ORLI10G Overview (continued)
Receive Path
The 16-bit receive data is deMUXed in the embedded
core to a single 128-bit or 64-bit data bus and passed
to the FPGA logic. The lowest-order LVDS input clock
(rx_clk_in[0]) is used as the receive clock for all 16 data
bits (the other three LVDS input clock pairs should be
tied low). This clock is divided down in the core by 8 (for
16-bit to 128-bit deMUX) or by 4 (for 16-bit to 64-bit
deMUX) and passed to the FPGA logic with the data.
The ORLI10G supports transmit and receive data rates
up to 667 Mbits/s. Therefore, the total data rate for this
mode is 667 Mbits/s x 16 or 10.672 Gbits/s.
2.5G Mode
In 2.5G (or quad channel) mode, the 16 LVDS transmit
data outputs are assumed to be four 4-bit data buses
with four LVDS clocks provided off chip for each data
bus. Likewise, the 16 LVDS receive data inputs are
assumed to be four independent 4-bit data buses with
four LVDS asynchronous input clocks provided for each
data bus.
Transmit Path
In 2.5G mode, the transmit data from the FPGA logic is
passed to the embedded core as four separate 32- or
16-bit buses. A separate clock for each of the four bus-
ses is also passed to the core. An off-chip transmit ref-
erence clock is divided down in the core by 8 (for each
32 to 8-bit MUX) or by 4 (for each 16 to 4 MUX). This
divided down clock is used to resynchronize the output
data and clocks. All four transmit clock outputs are
therefore synchronized.
Receive Path
Each of the four 4-bit receive data buses are deMUXed
in the embedded core to one of four independent 32- or
16-bit data buses and passed to the FPGA logic. The
four receive clock inputs are divided down in the core
by 8 (for each 4- to 32-bit deMUX) or by 4 (for each 4-
to 16-bit deMUX) and each divided clock is passed to
the FPGA logic with its associated data bus. All four
data paths act as separate data interfaces that are
asynchronous to each other.
The ORLI10G supports transmit and receive data rates
up to 667 Mbits/s. Therefore, the total data rate each of
the quad channels is thus 667 Mbits/s x 4 or
2.5 Gbits/s.
Figure 2 shows a representation of the 10G and 2.5G
modes in both transmit and receive directions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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