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Table of Contents
Contents
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Contents
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2
Agere Systems Inc.
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
Introduction..................................................................1
Embedded Function Features .....................................4
Intellectual Property Features......................................4
Programmable Features..............................................4
Programmable Logic System Features .......................6
Description...................................................................7
FPSC Definition .........................................................7
FPSC Overview .........................................................7
FPSC Gate Counting ................................................7
FPGA/Embedded Core Interface ..............................7
ORCA Foundry Development System ......................7
FPSC Design Kit .......................................................8
FPGA Logic Overview ...............................................8
PLC Logic ..................................................................8
Programmable I/O .....................................................9
Routing ......................................................................9
System-Level Features..............................................10
Microprocessor Interface .........................................10
System Bus .............................................................10
Phase-Locked Loops ..............................................10
Embedded Block RAM ............................................10
Configuration ...........................................................11
Additional Information .............................................11
ORLI10G Overview ...................................................11
Device Layout .........................................................11
10G Mode ...............................................................11
2.5G Mode ..............................................................12
Receive Path ...........................................................15
Transmit Path ..........................................................17
ORLI10G Demultiplexer Detail ..................................19
ORLI10G Multiplexer Detail.......................................25
ORLI10G Embedded PLLs........................................31
LI Circuit Specifications .............................................33
Power Supply Decoupling LC Circuit ......................33
XGMII ORCA 4E Receive Analysis ...........................34
XGMII Considerations .............................................34
Absolute Maximum Ratings.......................................35
Recommended Operating Conditions .......................35
Embedded Core LVDS I/O ........................................36
LVDS Receiver Buffer Requirements ......................37
Timing Characteristics ...............................................38
Receive/Transmit Input Data/Sync Interface ...........38
Transmit (Line)/Receive (System)
STS-48/STS-192 (2.5G/10G) Data Outputs ..........39
Input/Output Buffer Measurement Conditions
(On-LVDS Buffer) ......................................................40
LVDS Buffer Characteristics......................................41
Termination Resistor ...............................................41
LVDS Driver Buffer Capabilities ..............................41
Pin Information ..........................................................42
Package Pinouts .................................................... 47
Package Thermal Characteristics Summary ............ 67
ΘJA ......................................................................... 67
ψJC ........................................................................ 67
ΘJC ........................................................................ 67
ΘJB ........................................................................ 67
FPSC Maximum Junction Temperature ................. 67
Package Thermal Characteristics............................. 68
Heat Sink Vendors for BGA Packages ..................... 68
Package Coplanarity ................................................ 68
Package Parasitics ................................................... 69
Package Outline Diagrams....................................... 70
Terms and Definitions ............................................ 70
416-Pin PBGAM ..................................................... 71
680-Pin PBGAM ..................................................... 72
Hardware Ordering Information ................................ 73
Software Ordering Information ................................. 73