參數(shù)資料
型號(hào)： ORLI10G-1BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 34/76頁
文件大?。?/td> 1222K
代理商： ORLI10G-1BM680
4
Lattice Semiconductor
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
Embedded Function Features
■
Provides a line interface-to-interface with various
system standards such as OC-192/STM-64
SONET/SDH, quad OC-48/STM-16 10 Gbits/s Ether-
net, and 10 Gbits/s OTN (digital wrapper/strong FEC)
or 12.5 Gbits/s SuperFEC.
■
Embedded PLLs with programmable M/N multiplica-
tion/division values provide for exible data rate con-
version between line side and system side.
■
Line-side provides for 16-bit LVDS data with multiple
line frequencies supported up to 850 MHz, depend-
ing on system standard.
■
Line-side interface, including timing and jitter speci-
cations, compliant to OIF 99.102.5 standard.
■
Receive-side interface can be split into four separate
asynchronous 2.5 Gbits/s interfaces (4-bit LVDS data
interface for each) with a separate clock for each for
transfer to the FPGA logic.
■
Data and clock rates divided by 4 or 8 for use in
FPGA logic.
■
Direct interface to Agere's 10 Gbits/s MUX
(TTRN0110G) and deMUX (TRCV0110G) or
12.5 Gbits/s MUX (TTRN01126) and deMUX
(TRCV01126) for XSBI, SFI-4, or SuperFEC applica-
tions.
■
LVDS I/Os compliant with EIA-644 support hot
insertion. All embedded LVDS I/Os include both input
and output on-board termination to allow high-speed
operation.
■
Low-power LVDS buffers.
Intellectual Property Features
Programmable logic provides a variety of yet-to-be
standardized interface functions, including the following
IP core functions:
■
10 Gbits/s Ethernet, as dened by IEEE 802.3ae:
— XGMII for interfacing to 10 Gbits/s Ethernet
MACs. XGMII is a 156 MHz double data rate par-
allel short-reach (typically less than 2 in.) intercon-
nect interface.
— Elastic store buffers for clock domain transfer
to/from the XGMII interface.
— X59 + X39 + X1 scrambler/descrambler for
10 Gbits/s Ethernet.
— 64b/66b encoders/decoders for 10 Gbits/s Ether-
net.
■
POS-PHY4 interface for 10 Gbits/s SONET/SDH and
OTN systems and some 10 Gbits/s Ethernet sys-
tems.
■
Quad 2.5 Gbits/s SONET/SDH to 10 Gbits/s
SONET/SDH MUX/deMUX functions.
■
66-bit word aligner and 64b/66b receive path
decoder, 64b/66b transmit path encoder, and
66b/64b transmit path conversion for Ethernet over-
head bits.
Programmable Features
■
High-performance programmable logic:
— 0.16 m 7-level metal technology.
— Internal performance of >250 MHz.
— 400k usable system gates.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V opera-
tion) translates to greater performance.
■
Traditional I/O selections:
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)
I/Os.
— Per pin selectable I/O clamping diodes provide 3.3
V PCI compliance.
— Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew limited).
— Fast-capture input latch and input ip-op (FF)
latch for reduced input setup time and zero hold
time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two input function generator in output path.
■
New programmable high-speed I/O:
— Single-ended: GTL, GTL+, PECL, SSTL3/2 (class
I and II), HSTL (Class I, III, IV), ZBT, and DDR.
— Double-ended: LVDS, bused-LVDS, LVPECL. Pro-
grammable (on/off) internal parallel termination
(100 ) also supported for these I/Os.
■
New capability to (de)multiplex I/O signals:
— New DDR on both input and output at rates up to
350 MHz (700 MHz effective rate).
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 50 MHz internal to 200 MHz I/O).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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