參數(shù)資料
型號(hào): ORLI10G-1BM416I
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝: PLASTIC, MULTILAYER, BGA-416
文件頁(yè)數(shù): 56/74頁(yè)
文件大?。?/td> 1411K
代理商: ORLI10G-1BM416I
6
Agere Systems Inc.
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
Programmable Logic System Features
s
PCI local bus compliant for FPGA I/Os.
s
Improved PowerPC*860 and PowerPC II high-speed
synchronous microprocessor interface can be used
for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA logic, RAMs, and embedded stan-
dard-cell blocks. Glueless interface to synchronous
PowerPC processors with user-configurable address
space provided.
s
New embedded AMBA specification 2.0 AHB sys-
tem bus (ARM processor) facilitates communica-
tion among the microprocessor interface,
configuration logic, embedded block RAM, FPGA
logic, and embedded standard-cell blocks.
s
New network PLLs meet ITU-T G.811 specifications
and provide clock conditioning for DS-1/E-1 and
STS-3/STM-1 applications.
s
Flexible general-purpose PPLLs offer clock multiply
(up to 8x), divide (down to 1/8x), phase shift, delay
compensation, and duty-cycle adjustment combined.
s
Variable-size bused readback of configuration data
capability with the built-in microprocessor interface
and system bus.
* PowerPC is a registered trademark of International Business
Machines, Inc.
AMBA is a trademark and ARM is a registered trademark of
Advanced RISC Machines Limited.
s
Internal, 3-state, and bidirectional buses with simple
control provided by the SLIC.
s
New clock routing structures for global and local
clocking significantly increases speed and reduces
skew (<200 ps for OR4E4).
s
New local clock routing structures allow creation of
localized clock trees.
s
Two new edge clock routing structures allow up to
seven high-speed clocks on each edge of the device
for improved setup/hold times on input pins and
clock-to-out times on output pins (and both improve-
ments for bidirectional pins).
s
New double-data rate (DDR) and zero-bus turn-
around (ZBT) memory interfaces support the latest
high-speed memory interfaces.
s
New 2x/4x uplink and downlink I/O capabilities inter-
face high-speed external I/Os to reduced-speed
internal logic.
s
ORCA Foundry development system software. Sup-
ported by industry standard.
s
CAE tools for design entry, synthesis, simulation, and
timing analysis.
s
Meets universal test and operations PHY interface
for ATM (UTOPIA) Levels 1, 2, and 3 as well as POS-
PHY3. Also meets proposed specifications for UTO-
PIA Level 4 and POS-PHY4 for 10 Gbits/s interfaces.
s
Meets POS-PHY3 (2.5 Gbits/s) and POS-PHY4
(10 Gbits/s) interface standards for packet-over-
SONET as defined by the Saturn Group.
相關(guān)PDF資料
PDF描述
ORLI10G-1BMN416I FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-2BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
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