參數(shù)資料
型號(hào)： ORLI10G-1BM416I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, MULTILAYER, BGA-416
文件頁(yè)數(shù)： 28/74頁(yè)
文件大?。?/td> 1411K
代理商： ORLI10G-1BM416I
34
Agere Systems Inc.
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
XGMII ORCA 4E Receive Analysis
XGMII Considerations
The stringent 10 Gbit media independent interface specifications from the IEEE 802.3ae standards are met in the
FPGA side of the ORLI10G device. Figure 18 and Table 3 show a simplified block diagram for this interface and the
receive voltage levels for the HSTL inputs to the ORLI10G device.
The ORLI10G device meets the 480 ps input setup time and 480 ps input hold time requirements for the XGMII
receiver inputs into the FPGA side of the FPSC with the embedded IO DDR cells and the embedded PLLs on the
FPGA side of the FPSC. The PLLs are not used on input due to this being a forward clocked interface. The
ORLI10G meets the clock-to-out specification on the XGMII DDR outputs by using the output shift register to pro-
duce a nonduty cycle dependent output. The output clock is then centered around this data eye using internal
PLLs.
There are two considerations to note about the pinout location of the XGMII input clocks.
1.
The XGMII input clocks must be located at the C pad of the programmable I/O Cells (PICs). In the pinout
tables, the pads are labelled on a pin-by-pin basis. For example, a pin whose pad is referenced as PL1C can
be used as an XGMII input clock, but pins referenced as PL1A, PL1B, or PL1D cannot be used as an XGMII
input clock.
2.
The XGMII input data pins can be no further then six PICs away from the XGMII input clock pin. This means
that in the 416 PBGA package, the clock needs to be driven on two pins to be able to clock in the 32-bit XGMII
input data bus.
The only considerations to note about the XGMII output transmit clock is that it needs to be phase-locked with an
embedded PLL in the FPGA side of the FPSC.
Due to the strict pinout locations mentioned above, when implementing a XGMII interface, the microprocessor
interface (MPI) will not be available in the 416 PBGA and 680 PBGA packages.
1550(F)
Figure 18. Simplified XGMII Block Diagram
CUSTOMER
CHIP
FPGA
HSTL
DATA
CLOCK
VDDIO
VDD15
VDDIO = 1.5 V NOM
INPUT
RECEIVERS
HSTL
VDDIO = 1.5 V NOM
OUTPUT
DRIVERS
VREF
VDDIO
÷ 2
相關(guān)PDF資料
PDF描述
ORLI10G-1BMN416I FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-2BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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