參數(shù)資料
型號： ORLI10G-1BM416I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, MULTILAYER, BGA-416
文件頁數(shù)： 34/74頁
文件大?。?/td> 1411K
代理商： ORLI10G-1BM416I
4
Agere Systems Inc.
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
Embedded Function Features
s
Provides a 10 Gbits/s line interface-to-interface with
various system standards such as OC-192/STM-64
SONET/SDH, Quad OC-48/STM-16 10 Gbits/s
Ethernet, and 10 Gbits/s OTN (digital wrapper/strong
FEC).
s
Embedded PLLs with programmable M/N multiplica-
tion/division values provide for flexible data rate con-
version between line side and system side.
s
Line side provides for 16-bit LVDS data with multiple
line frequencies supported up to 667 MHz.
s
Line-side interface, including timing and jitter specifi-
cations, compliant to OIF 99.102.5 standard.
s
Receive-side interface can be split into four separate
asynchronous 2.5 Gbits/s interfaces (4-bit LVDS data
interface for each) with a separate clock for each for
transfer to the FPGA logic.
s
Data and clock rates divided by 4 or 8 for use in
FPGA logic.
s
Direct interface to Lucent’s 10 Gbits/s MUX
(TTRN0110G) and deMUX (TRCV0110G).
s
LVDS I/Os compliant with EIA*-644, support hot
insertion. All embedded LVDS I/Os include both input
and output on-board termination to allow high-speed
operation.
s
Low-power LVDS buffers.
s
Built-in boundary scan (IEEE 1149.1 JTAG).
Intellectual Property Features
Programmable logic provides a variety of yet-to-be stan-
dardized interface functions, including the following IP
core functions:
s
10 Gbits/s Ethernet as defined by IEEE 802.3ae:
— XGMII for interfacing to 10 Gbits/s Ethernet MACs.
XGMII is a 156 MHz double data rate parallel
short-reach (typically less than 2 inches) intercon-
nect interface.
— Elastic store buffers for clock domain transfer to/
from the XGMII interface.
— X58 + X19 + X1 scrambler/descrambler for
10 Gbits/s Ethernet.
— 66-bit word aligner and 64b/66b receive path
decoder, 64b/66b transmit path encoder, and 66b/
64b transmit path conversion for Ethernet over-
head bits.
* EIA is a registered trademark of Electronic Industries Association.
— 10 Gbits/s media access controller (MAC) can be
implemented in a separate FPGA, FPSC, or
ASIC.
s
POS-PHY4 interface for 10 Gbits/s SONET/SDH and
OTN systems and some 10 Gbits/s Ethernet sys-
tems.
s
Quad 2.5 Gbits/s SONET/SDH to 10 Gbits/s SONET/
SDH MUX/deMUX functions.
Programmable Features
s
High-performance programmable logic:
— 0.13 m 7-level metal technology.
— Internal performance of >250 MHz.
— 400k usable system gates.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V oper-
ation) translates to greater performance.
s
Traditional I/O selections:
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast & slew-limited).
— Fast-capture input latch and input flip-flop
(FF) latch for reduced input setup time and zero
hold time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two input function generator in output path.
s
New programmable high-speed I/O:
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I & II), HSTL (Class I, III, IV), ZBT, and DDR.
— Double-ended: LVDS, bused-LVDS, LVPECL.
— Customer defined: ability to substitute arbitrary
standard-cell I/O to meet fast moving standards.
s
New capability to (de)multiplex I/O signals:
— New DDR on both input and output at rates up to
311 MHz (622 MHz effective rate).
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 50 MHz internal to 200 MHz I/O).
相關(guān)PDF資料
PDF描述
ORLI10G-1BMN416I FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-2BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
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ORLI10G-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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