參數(shù)資料
型號(hào)： ORLI10G-1BM416
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, BGA-416
文件頁(yè)數(shù)： 26/76頁(yè)
文件大?。?/td> 1222K
代理商： ORLI10G-1BM416
32
Lattice Semiconductor
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
ORLI10G Embedded Programmable PLLs Specications
Table 2. Programmable PLL Specications
Notes:
Multiplication and division values can both be used on one PLL output (example 3/4x).
For more information about the HPPLL, see the Series 4 PLL Application Note.
ORLI10G Reset Requirements
Both the embedded core portion and the FPGA portion are reset at powerup. The embedded core is also reset, as
shown in Table 3, based on other conditions. All resets to the core can either be asynchronous or asynchronous on
with a synchronous release. Asynchronous resets must be held in reset for at least 8 ns. Two signals from the
FPGA logic can also reset the embedded core: the global set/reset (GSRN) which can be inhibited, and a signal
routed from the FPGA general routing. Both of these affect both the TX and RX reset simultaneously. Table 3 also
shows the conditions upon which the I/O are 3-stated.
Table 3. ORLI10G Reset Requirements
Typically, the following reset sequence should be followed for the ORLI10G:
■
Place the device in reset by driving RESET_TX = 1 and RESET_RX = 1 (or FPGA_RESET signal = 1), and by
placing the FPGA portion into reset.
■
Release the embedded core from reset by driving RESET_TX = 0 and RESET_RX = 0 and FPGA_RESET
signal = 0).
■
Release the FPGA portion from reset.
Parameters
Min
Nom
Max
Unit
VDD15
1.425
1.5
1.575
V
VDD33
3.0
3.3
3.6
V
Operating Temperature
–40
—
125
C
Input Clock Frequency
60
—
420
MHz
Input Duty Cycle
30
—
70
%
Output Clock Frequency
7.5
—
420
MHz
Output Duty Cycle
45
50
55
%
Lock Time
—
<50
—
s
Frequency Multiplication (TX1_PLL and RX1_PLL)
2x, 3x, 4x, 5x, 6x, 7x, 8x
—
Frequency Division (TX1_PLL and RX1_PLL)
1/8x, 1/7x, 1/6x, 1/5x, 1/4x, 1/3x, 1/2x
—
Duty Cycle Adjust of Output Clock(s)
12.5, 25, 37.5, 50, 62.5, 75, 87.5
%
Delay Adjust of Output Clock
0, 45, 90, 135, 180, 225, 270, 315
degrees
Phase Shift Between VCO and VCOP
0, 45, 90, 135, 180, 225, 270, 315
degrees
Condition
TX MUX Block
TX PLL
RX DeMUX Block
RX PLL
Embedded I/O
Powerup
Reset
3-state
FPGA Conguration
Reset
Active
FPGA GSRN
Reset
Active
FPGA_RESET Signal
Reset
Active
TS_ALL Pin = 1
—
3-state
RESET_TX Pin = 1
Reset
—
Active
RESET_RX Pin = 1
—
Reset
Active
PWRON Pin = 1
—
Powerdown
—
Powerdown
Active
相關(guān)PDF資料
PDF描述
ORLI10G-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-2BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-3BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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